The enhanced ALM also:
Packs six percent more logic compared to the previous-generation ALM found in Stratix IV devices.
Implements select 7-input LUT-based functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core utilization.
Provides 4 registers per 8-input fracturable LUT. This enables Stratix V devices to maximize core performance at higher core logic utilization and provide easier timing closure for register-rich and heavily pipelined designs.
Quartus® II software leverages the Stratix V ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. Quartus II software simplifies design reuse as it automatically maps legacy Stratix designs into the new ALM architecture.
The ALMs are routed with the MultiTrack interconnect architecture, enabling a Stratix series FPGA to implement high-speed logic, arithmetic, and register functions.
For more details on the logic architectures of previous Stratix series FPGA families, see the respective handbook chapters from the Device Documentation section of our literature page.
Table 1 outlines the features and benefits of moving to the enhanced ALM structure in Stratix V FPGAs.