Stratix II: 8Input Fracturable LUT in the ALM
The new and innovative logic structure of Stratix^{®} II devices delivers unprecedented performance and logic efficiency. This logic structure is built from basic logic units known as adaptive logic modules (ALMs). Each ALM contains a variety of (lookup table) LUTbased resources, two full adders, carrychain segments, two flipflops, and many additional logic enhancements that can be flexibly divided into two adaptive LUTs (ALUTs). Logical functions with up to 7 inputs and complex logicarithmetic functions can be implemented in one ALM.
Research has shown that lookup tables (LUTs) with a higher input count provide better performance in FPGA designs. At the same time, logic fabrics that use arrays of 4 or less input LUTs provide better area efficiency. The new Stratix II logic structure achieves the best of both worlds—its performance is comparable to 7input LUT based FPGAs and its logic efficiency is better than programmable devices using a 4input LUT. Figure 1 shows the different LUT configurations that a single ALM can support and Table 1 describes each ALM configuration.
Figure 1. Stratix II ALM Configurations
Table 1. Stratix II ALM Configurations
Example 
Description 

The logic structure in Stratix II devices can implement two independent 4input (or smaller) LUTs (4LUT) per ALM. This configuration is “backwardcompatible” and ideal for migrating a design that is optimized for traditional 4input LUT FPGAs to the Stratix II device family. 

Stratix II ALMs can implement a 5input LUT (5LUT) and a 3input LUT (3LUT) per ALM. The inputs to the two LUTs are independent of each other. The 3input LUT can be used to implement any logic function that has three or fewer inputs. Therefore, a 5input LUT and 2input LUT are also allowed. 

The ALMs within the Stratix II architecture can be configured to implement a 5input LUT and a 4input LUT per ALM. One of the inputs must be shared between the two LUTs. The 5input LUT has up to four independent inputs. The 4input LUT has up to three independent inputs. The sharing of inputs between LUTs is very common in FPGA designs, and Quartus^{®} II software will automatically seek logic functions that are structured in this manner. 

Stratix II ALMs can implement two 5input LUTs per ALM. In this case, two of the inputs between the LUTs are common and up to three independent inputs are allowed for each 5input LUT. 

Stratix II ALMs support any 6input logic function per ALM. If there are two 6input functions that have the same logic operation and four shared inputs, then these two 6input functions can be implemented in one Stratix II ALM. For example, a 4x2 crossbar switch that has four data input lines and two sets of unique select signals requires 4 LEs in a Stratix device. In a Stratix II device, this same function only consumes one ALM. In another example, a single Stratix II ALM can implement two 6input AND gates that have four common inputs. The same function in a Stratix device requires three LEs. 

In the extended mode, the Stratix II logic structure can perform certain logical functions with up to 7 inputs per ALM. Quartus II software can automatically recognize the applicable 7input function and fit it into an ALM. For detailed information about the types of 7input functions that can be implemented within an ALM, refer to the Stratix II Device Handbook. 
ALM Performance Advantages
When implementing a logic function with a large number of inputs, the logic function is decomposed into smaller cascading logic blocks that are restricted by the size (number of inputs) of the lookup table (LUT) in the FPGA. Each cascading LUT is considered a logic level. The number of logic levels and the programmable routing segments on the critical path dictate the performance of the system. More logic levels and routing segments mean longer logic propagation delay and slower system performance.
The Stratix II ALM goes beyond the simple 4inputLUT structure and extends the logic capacity to efficiently construct any logic functions with 5 or 6 inputs. See Figure 2 for a comparison of a generic 4input LUT logic structure verses an ALMbased logic structure. When ALMs are configured in the extended LUT mode, many 7input functions can be implemented by each ALM. With ALM’s ability to implement functions with higher input counts, the Stratix II logic structure offers an average performance improvement of 50 percent as compared to Stratix by:
 Reducing the number of logic levels required for the overall combinatorial logic
 Reducing the extra programmable routing needed in the 4inputLUT implementation
 Reducing the stress on the demand for general routing resources
Figure 2. Stratix II ALM’s Native 6InputLUT Support Reduces Logic Levels and Programmable Routing Delays
ALM Logic Efficiency Advantages
The ALM’s flexible logic structure gives Stratix II FPGAs an average 25 percent more efficient use of logic over prior FPGA families. A key innovation lies in the ability of Stratix II ALMs to implement two LUTs of the same or different sizes to exactly match a design’s combinational logic that is decomposed into smaller and differentsized logic blocks.
Quartus II software can automatically utilize the full potential of the Stratix II ALM to implement LUTs of different sizes. As shown in Figure 3, when implementing a function of three variables in the traditional 4input LUT structure, the fourth, unused port is wasted. However, for a Stratix II ALM, after implementing a 3variable function, it can still be used to implement a 5input function.
Figure 3. Stratix II Logic Efficiency Example
The Stratix II logic structure further improves logic efficiency, allowing the implementation of two 6input LUTs that perform the same logic operation in one ALM. As shown in Figure 4, a 4x2 crossbar switch takes four LUTs in a generic 4input LUT architecture; however, the same design will fit in one Stratix II ALM.
Figure 4. Generic 4Input LUT Logic Structure vs. Stratix II 4x2 Crossbar Switch Logic Structure
The superior performance achieved by the ability to implement wideinput LUTs in one Stratix II ALM combined with the exceptional logic efficiency make the Stratix II device family the ideal choice for highperformance and highdensity designs.
Table 2. Learn More about Stratix II FPGAs
Topic  Description 
Performance Comparison  Compare Stratix II Performance with Competing Devices 
Architecture  FPGA Architecture White Paper 
Stratix II vs. Virtex5 Logic Efficiency  
Performance and Logic Efficiency Analysis White Paper  
Design Building Blocks  
Embedded Adders  
DSP  DSP Blocks 
DSP Performance Center 