Intel is committed to providing intellectual property (IP) cores that work seamlessly with Intel® FPGA tools or interface specifications, making it easier for users to complete their designs quickly and easily. Intel may award IP cores one or more of the following certifications.
Intel awards the Qsys Compliant certification to IP cores that seamlessly integrate with the Platform Designer included in the Intel Quartus® Prime design software. Qsys Compliant cores support the interconnect which leverages the Avalon® Streaming and Memory-Mapped interfaces. Search the online catalog to see which Intel and Design Solutions Network member IP cores are Qsys Compliant. Refer to the Qsys Compliant web page for more information.
|Intel awards the DSP Builder Ready certification to IP cores that have plug-and-play integration with the DSP Builder for Intel FPGAs software. The DSP Builder for Intel FPGAs shortens digital signal processing (DSP) design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. You can combine existing MATLAB/Simulink blocks with the DSP Builder for Intel FPGAs or Intel FPGA IP blocks to verify system-level specifications and generate hardware implementations. After installing DSP Builder Ready IP, a symbol appears in the Simulink library browser under the DSP Builder for Intel FPGAs Blockset.|
|Intel awards I-Tested certification to IP cores that have been tested to be compliant with protocol standards. These cores are verified in an Intel FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the necessary protocols. Refer to the I-Tested web page for more information about I-Tested IP cores.|