Intel's complete memory interface design solutions address today's high-speed memory interface challenges. Specifically, Intel provides solutions for a host of mainstream SDRAM and SRAM memory protocols, as well as serial memory technologies such as Hybrid Memory Cube (HMC) and Bandwidth Engine. Our memory interface solutions include high-performance memory controller options, memory PHY options, and multi-port front-end options. These solutions support error correction codes (ECC).
Intel® Stratix® 10 and Intel Arria® 10 FPGAs and SoCs provide high performance of memory interfaces on 14 nm and 20 nm nodes respectively with hardened memory controllers. These hard memory controllers offer several advantages over soft memory controller options, and some of the benefits include:
- Enables shorter engineering cycles and faster time to market because timing is pre-closed in the hardened logic
- Saves user logic resources
- Achieves higher performance in terms of fMAX, efficiency, and latency
- Allows for a lower power memory interface solution
Arria V and Cyclone® V devices also support hard memory interfaces. Typical expected performance and utilization figures for these hard controllers and PHYs are provided in the External Memory Interface Handbook.
Our solutions are provided as either advanced device architectures, customizable Intel FPGA IP functions in the Intel Quartus® Prime design software, dynamically generated design examples, demonstration boards, and/or simulation models. All of which are accompanied by a rich set of technical documentation.
The Board Skew Parameter Tool (XLS) enables easy and precise board skew parameter calculations while saving crucial design time.