External Memory Interface

Overview

Intel®'s (formerly Altera) complete memory interface design solutions address today's high-speed memory interface challenges. Specifically, Intel provides solutions for a host of mainstream SDRAM and SRAM memory protocols, as well as serial memory technologies such as Hybrid Memory Cube (HMC) and Bandwidth Engine.  Our memory interface solutions include high-performance memory controller options, memory PHY options, and multi-port front-end options. These solutions support error correction codes (ECC).

Arria® 10 FPGAs and SoCs provide the highest performance of memory interfaces with a new innovative hardened memory controller. This hard memory controller offers several advantages over soft memory controller options, and some of the benefits include:

  • Enables shorter engineering cycles and faster time to market since timing is pre-closed in the hardened logic
  • Saves user logic resources
  • Achieves higher performance in terms of fMAX, efficiency, and latency 
  • Allows for a lower power memory interface solution  

Arria V and Cyclone® V devices also support hard memory interfaces. Typical expected performance and utilization figures for these hard controllers and PHYs are provided in the External Memory Interface Handbook.

Our solutions are provided as either advanced device architectures, customizable MegaCore® functions in the Quartus® Prime design software, dynamically generated design examples, demonstration boards, and/or simulation models. All of which are accompanied by a rich set of technical documentation.

The Board Skew Parameter Tool (XLS) enables easy and precise board skew parameter calculations while saving crucial design time.

Table 1 lists external memory interfaces supported by Intel FPGA devices. Get more information using our External Memory Interface Spec Estimator.

Table 1. External Memory Interface Support

Device Memory Type
DDR4 DDR3 DDR2 LPDDR3 LPDDR2 RLDRAM3 RLDRAM2 QDRIV QDRII+
Xtreme
QDRII+ QDRII
Stratix® 10 (1) 2,666 
Mbps

1,333 
MHz
2,133
Mbps

1,066
MHz
- 1,600
Mbps

800
MHz
- 2,400
Mbps

1,200
MHz
- 2,133
Mtps

1,066
MHz
1,266
Mtps

633
MHz
1,100
Mtps

550
MHz
700
Mtps

350
MHz
Stratix V - 1,866
Mbps

933
MHz
1,066
Mbps

400
MHz
- - 1,600
Mbps

800
MHz
1,067
Mbps

533
MHz
- - 2,200
Mtps

550
MHz
1,400
Mtps

350
MHz
Stratix IV - 1,066
Mbps

533
MHz
800
Mbps

400
MHz
- - - 1,067
Mbps

533
MHz
- - 2,200
Mtps

550
MHz
1,400
Mtps

350
MHz
Arria 10 2,400 
Mbps

1,200 
MHz
2,133
Mbps

1,066
MHz
- 1,600
Mbps

800
MHz
- 2,400
Mbps

1,200
MHz
- 2,133
Mtps

1,066
MHz
1,266
Mtps

633
MHz
1,100
Mtps

550
MHz
 667 
Mtps 

 333 
MHz
Arria V - 1,334
Mbps

667
MHz
800
Mbps

400
MHz
- 800
Mbps

400
MHz
- 800
Mbps

400
MHz
- - 1,600
Mtps

400
MHz
1,600
Mtps

400
MHz
Arria V GZ - 1,600
Mbps

800
MHz
800
Mbps

400
MHz
- - 1,334
Mbps

667
MHz
700
Mbps

350
MHz
- - 2,000
Mtps

500
MHz
1,400
Mtps

350
MHz
Cyclone V - 800
Mbps

400
MHz
800
Mbps

400
MHz
- 667
Mbps

333
MHz
- - - - - -
Cyclone IV - - 400
Mbps

200
MHz
- - - - - - - 668
Mtps

167
MHz
MAX® 10  - 606
Mbps
303
MHz
400
Mbps
200
MHz
- 400
Mbps
200
MHz
- - - - - -
Notes:
  1. Pending characterization.

Continuously advancing semiconductor process technologies have increase component integration, functionality, and performance in embedded systems. While increased capabilities reap huge rewards, one side effect of higher-performance memory systems is that more attention must be paid to the probability of soft errors.

Decreasing supply voltages cause integrated circuits to be more susceptible to various types of electromagnetic and particle radiation. As DRAM memory size in embedded systems grows to 100s of megabytes, soft errors due to alpha particles that occurs naturally may exceed acceptable levels. As interface speeds exceed 1 Gbps, excessive noise and jitter may cause errors in the transmission lines to and from the external memory.

Error Resilience Through Error Correction Code

Driven by the increasing probability of soft errors, many designers are considering to add ECC to external DDR memory. ECC allows correction of single bit errors and drastically reduces the chance of a system failure. Intel FPGA SoCs are well positioned to support ECC, as all required logic functions are integrated into the device. ECC on external memory can be enabled simply by extending the width of the DDR memory, as shown in Figure 1.

Figure 1 Typical External DDR Memory Architecture

System-Level Approach to Error Resilience

SoCs extend support toward error resilience by including support for ECC on its large internal memories, specifically the level 2 cache of 512 KB and data buffers in on-chip peripherals.

High-performance embedded systems often use a 32 bit data bus to external DDR to obtain high throughput and frequently have a need for error resilience through ECC. The Intel FPGA SoC provides the high performance and reliable combination of ECC and 32 bit interfacing.

The FPGA External Memory Interface Spec Estimator, a parametric tool, allows you to find and compare the performance of the supported external memory interfaces in our FPGAs. You’ll have the ability to filter down to specific performances based on your search specifications, and then compare performances across FPGAs side-by-side by filtering the criteria you choose for analysis. The External Memory Interface Spec Estimator supports DDR4 SDRAM, DDR3 SDRAM, DDR2 SDRAM, DDR SDRAM, LPDDR3 SDRAM, LPDDR2 SDRAM, RLDRAM 3, RLDRAM 2, QDR II SRAM, QDR II+ SRAM, QDR II+ Xtreme SRAM, and QDR IV SRAM interfaces.

The stated performances are the maximum clock rates supported in Intel FPGAs based on the listed features across supported high-speed memory standards.

The maximum clock rates are only estimates based on a standalone FPGA ALTMEMPHY or UniPHY with Nios®-Based Sequencer and High-Performance Controller II instance generated with the default controller parameters in the MegaCore intellectual property (IP). For the actual performance of your design, you must always compile and perform timing analysis for your design in Quartus Prime software.

The External Memory Interface Spec Estimator replaces the maximum clock rate tables in the Selecting Device, Memory Components, and IP(PDF) section in volume 1 of the External Memory Interfaces Handbook. The devices supported by the External Memory Interface Spec Estimator are the Stratix V, Stratix IV, Stratix III, Arria 10, Arria V, Arria II GZ, Arria II GX, Cyclone V, Cyclone IV, and Cyclone III device families.

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