To help shorten your design time, Altera® provides full production licenses for some of our most popular intellectual property (IP) cores (shown in Table 1) in the Altera IP Base Suite, which is free with Quartus® Prime Standard and Pro design software editions.

If you have an active license to Quartus Prime Standard Edition or Quartus Prime Pro Edition design software, simply log on to the Self-Service Licensing Center to generate your license file and take advantage of the IP Base Suite.

The IP Base Suite is also installed with Quartus Prime Lite Edition software. Full licenses to this suite are purchased separately. Contact your local Altera sales representative to learn more.

Questions? Please see IP Base Suite Questions and Answers.

Table 1. MegaCore® Functions in the IP Base Suite  

IP MegaCore Functions Description
FIR Compiler II

Over 12 major finite impulse response (FIR) filter architectures for use across multiple DSP applications. Generates bit-accurate and clock-cycle accurate models developed in Verilog, VHDL, MATLAB and provides coefficient generation. Provides significantly lower FPGA resource usage and increased performance than the original FIR Compiler for most FIR filter implementations. FIR filter performance, internal pipelining, and logic resource usage are optimized based on user inputs.

NCO Optimized for digital phase-locked loop (PLL) and digital interface functions. Supports multiple ROM-, CORDIC-, and multiplier-based architectures.
FFT A high-performance, highly parameterizable fast Fourier transform (FFT) processor. The FFT function implements a Radix-2/4 decimation-in-frequency FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation.

AXI BFM

 

 

The Mentor Graphics® AXI Verification IP Suite (Altera® Edition) provides bus functional models (BFMs) to simulate the behavior and to facilitate the verification of IP that conforms to the Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (AMBA® AXITM) Protocol. 

DDR2 SDRAM High-Performance Controller supporting UniPHY DDR2 SDRAM memory interface controller with integrated Qsys interface. Supports Altera's memory physical layer UniPHY.
DDR3 SDRAM High-Performance Controller supporting UniPHY DDR3 SDRAM memory interface controller with integrated Qsys interface. Supports Altera's memory physical layer UniPHY.
LPDDR2 SDRAM Controller supporting UniPHY

LPDDR2 SDRAM memory interface controller with integrated Qsys interface. Supports UniPHY.

QDR II/QDR II+ SRAM Controller supporting UniPHY QDR II/QDR II+ SRAM memory interface controller supports burst-of-2 and burst-of-4 QDR II devices. The controller also utilizes the low-latency UniPHY interface.
RLDRAM II Controller supporting UniPHY RLDRAM II memory interface controller supports common I/Os and separate I/Os in RLDRAM II devices. The controller also utilizes the low-latency UniPHY interface.
QDR II/QDR II+/QDR II+ Xtreme SRAM Controller supporting Arria 10 Devices  QDR II/QDR II+/QDR II+ Xtreme SRAM memory interface controller with integrated Qsus interface.  This controller support Arria 10 FPGAs and SoCs only.