FIR Compiler II Intel® FPGA IP Core

What's New for v17.0: Support for Intel® Stratix® 10 device WYSIWYGs to improve area and fMAX

Intel recommends the use of FIR Compiler II Intel FPGA IP core for new designs. The FIR Compiler II Intel FPGA IP core provides significantly lower FPGA resource usage and increased performance than the original FIR Compiler for most FIR filter implementations. The original FIR Compiler Intel FPGA IP core will continue to be supported for existing designs.

The FIR Compiler II Intel FPGA IP core generates finite impulse response (FIR) filters customized for Intel FPGAs. You can use the IP Toolbench interface to implement a variety of filter architectures, including fully parallel, serial, or multibit serial distributed arithmetic and multicycle fixed/variable filters. The FIR Compiler II Intel FPGA IP core also includes a coefficient generator.

The FIR Compiler II Intel FPGA IP core speeds your design cycle by:

  • Providing a fully integrated FIR filter development environment
  • Generating the coefficients needed to design custom FIR filters
  • Generating bit-accurate and clock-cycle-accurate FIR filter models in Verilog HDL, VHDL, and MATLAB
  • Automatically generating the code required for the Intel Quartus® Prime design software to synthesize high-speed, area-efficient FIR filters of various architectures
  • Creating Quartus Prime test vectors to test the FIR filter's impulse response
  • Generating a VHDL testbench for all architectures

The FIR Compiler II Intel FPGA IP core generated by this compiler also:

  • Supports a variety of distributed arithmetic and multiplier-based filter architectures up to 2,047 taps
  • Generates MATLAB simulation models and testbench
  • Generates a VHDL testbench for all architectures
  • Is highly optimized for Intel FPGA device architectures
  • Provides precision control of chip resource utilization
    • Utilizes logic cells, M512, M4K, M-RAM, MLAB, M9K, or M144K blocks for data storage
    • Utilizes logic cells, M512, M4K, MLAB, or M9K blocks for coefficient storage

Typical expected performance and utilization figures for this core are provided in the FIR Compiler II Intel FPGA IP Core User Guide.

For technical support on this IP core, please visit mySupport. You may also search for related topics on this function in the Knowledge Center and the following documentation: