High-Speed Reed Solomon MegaCore IP

The Intel® FPGA High-Speed Reed-Solomon MegaCore® intellectual property (IP) (encoder/decoder) uses a large parallel architecture to achieve a large throughput for applications that require 100 Gbps. The IP core is suitable for 10G (such as OTN) or 100G Ethernet (IEEE 802.3bj/bm) applications.

The High-Speed Reed-Solomon MegaCore IP has the following features:

  • Fully parameterizable:
    • Number of bits per symbol
    • Number of symbols per codeword
    • Number of check symbols per codeword
    • Field polynomial
  • Avalon® Streaming (Avalon-ST) interfaces
  • Testbenches to verify the IP core
  • IP functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators

Typical expected performance and utilization figures for this MegaCore function are provided in the High-speed Reed-Solomon IP Core User Guide.

For technical support on this IP core, please visit mySupport. You may also search for related topics on this function in the Knowledge Center.