Turbo IP MegaCore

from Intel® (formerly Altera)

The Turbo IP MegaCore® is a forward error correction code CODEC that supports the UMTS and LTE standards.

Turbo IP Core Features

  • 3GPP LTE compliant
  • 3GPP UMTS compliant with support for block sizes from 40 to 5,114
  • C/MATLAB bit-accurate models for performance simulation or register transfer level (RTL) test vector generation

Decoder Features

  • Successive Interface
  • Cancellation (SIC) for the LTE-A channel coding enhancement over LTE
  • Run time parameters for interleaver size and number of iterations
  • Early termination with cyclic redundancy check (CRC)
  • Compile time parameters for the number of parallel engines, choice of decoding algorithm, input precision, and output size
  • Double-buffering for reduced latency real-time applications, which allows the decoder to receive data while processing the previous data block
  • No external memory required

Encoder Features

  • 3GPP LTE and LTE-A compliant
  • 3GPP UMTS compliant with support for block sizes from 40 to 5,114
  • Run-time selectable interleaver block sizes
  • Code rate 1/3 only
  • Use external rate matching for other code rates
  • Double-buffering allows the encoder to receive data while processing the previous data block

Typical expected performance and utilization figures for this core are provided in the Turbo IP MegaCore User Guide (PDF).

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