Video and Image Processing Suite Intel® FPGA IP

Notice: The Frame Reader I function in the Video and Image Processing Suite have started the obsolescence process. Please refer to the product discontinuation notice, PDN1603.

The Intel® FPGA Video and Image Processing Suite is a collection of Intel FPGA IP functions that you can use to facilitate the development of custom video and image processing (VIP) designs. These Intel FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as video surveillance, broadcast, video conferencing, and medical and military imaging.
The Video and Image Processing Suite features cores that range from simple building block functions, such as color space conversion to sophisticated video scaling functions that can implement programmable polyphase scaling. Table 1 lists all the cores included in the Video and Image Processing Suite.

  • All the VIP cores use an open, low-overhead Avalon® Streaming (Avalon-ST) interface standard so that they can be easily connected
  • You can use VIP cores to quickly build a custom video processing signal chain using the Intel Quartus® Prime Lite or Standard Edition software and the associated Intel Platform Designer
  • You can mix and match VIP cores with your own proprietary intellectual property (IP)
  • You can use the Platform Designer to automatically integrate embedded processors and peripherals and generate arbitration logic
  • Capable of supporting 4K video

 

Video and Image Processing Suite Intel FPGA IP Functions

Intel FPGA IP Function

Description

2D FIR Filter Implements a 3x3, 5x5, or 7x7 finite impulse response (FIR) filter on an image data stream to smooth or sharpen images.
Alpha Blending Mixer and Mixer II Mixes and blends multiple image streams—useful for implementing text overlay and picture-in-picture mixing.
Avalon-ST Video Monitor Captures video data packets without adding additional delays and connect to trace system IP for collecting video trace data.
Avalon-ST Video Stream Cleaner Removes and repairs the non-ideal sequences and error cases
present in the incoming data stream to produce an output stream that complies with the implicit ideal use model.
Chroma Resampler Changes the sampling rate of the chroma data for image frames, for example from 4:2:2 to 4:4:4 or 4:2:2 to 4:2:0.
Clipper II Provide a way to clip video streams and can be configured at compile time or at run time.
Clocked Video Input (CVI), Clocked Video Input II (CVI II), Clocked Video Output (CVO) and Clocked Video Output II (CVO II) The Clocked Video Interface IP cores convert clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST video; and vice versa.
Color Plane Sequencer and Color Plane Sequencer II
Changes how color plane samples are transmitted across the Avalon-ST interface. This function can be used to split and join video streams, giving control over the routing of color plane samples.
Color Space Converter (CSC) and Color Space Converter II (CSC II) Convert image data between a variety of different color spaces such as RGB to YCrCb.
Control Synchronizer Synchronizes the changes made to the video stream in real time between two functions.
Deinterlacer Converts interlaced video formats to progressive video format using a motion adaptive deinterlacing algorithm. Also supports "bob" and "weave" algorithms.
Deinterlacer II Converts interlaced video formats to progressive video format using a motion adaptive deinterlacing algorithm. Also supports "bob" and "weave" algorithms, low-angle edge detection, 3:2 cadence detection, and low latency.
Broadcast Deinterlacer

Converts interlaced video to progressive video using high quality motion-adaptive algorithm.

Frame Buffer and Frame Buffer II Buffer video frames into external RAM. This core supports double or triple-buffering with a range of options for frame dropping and repeating.
Frame Reader Reads video from external memory and outputs it as a stream.
Gamma Corrector and Gamma Corrector II
Allows video streams to be corrected for the physical properties of display devices.
Interlacer and Interlacer II
Converts progressive video to interlaced video by dropping half the lines of incoming progressive frames.
Scaler II HDL code-based Scaler II Intel FPGA IP function uses less area than first-generation Scaler in the Video and Image Processing Suite while delivering higher performance. The Scaler II function further reduces required resources with new support of 4:2:2 chroma data sampling rate. Both linear and polyphase algorithms are available with new feature of edge adaptive algorithm to reduce blurriness while maintaining realism.
Switch and Switch II Allow video streams to be switched in real time.
Test Pattern Generator II Generate a video stream that contains still color bars for use as a test pattern.
Trace System Monitors captured data from video monitor and connects to host System Console via JTAG or USB for display

The following table shows the recommended order of learning materials: 

  Description

Intel FPGA Video and Image Processing Suite Solution Sheet

(PDF)

One sheet overview of the Video and Image Processing Suite including application segments, key features, and design solutions.

Video Systems 101

Video Systems 101

10 minutes

This video walks through some of the basics of video imaging and processing algorithms, connectivity, chroma sampling, and color formats.

Video Design Tutorial #1: Build Video Designs Quickly with Intel FPGA VIP & ALSE AVDB

7 minutes

This tutorial introduces the Intel FPGA Video and Image Processing Suite and ALSE AVDB development kit, and how they can be used to quickly build video designs. The tutorial also gives an overview and demonstration of a simple video design example utilizing the Video and Image Processing Suite on AVDB.

Video Design Tutorial #2: Video Design Basics & Intel FPGA Video Framework

31 minutes

This tutorial reviews several digital video design basics, as well as an overview of the Intel FPGA video framework, including Video and Image Processing Suite, Avalon interfaces, and Qsys system integration tool and how the video framework + ALSE AVDB development kit can accelerate the development of your video designs.

Video Design Tutorial #3: Hands-On Tutorial on Building Video Designs with Intel FPGA VIP and ALSE AVDB

21 minutes

This tutorial shows step-by-step instructions on building a simple video design example utilizing the Intel FPGA Video and Image Processing Suite on the ALSE AVDB development kit. The design example is available on the Intel FPGA Design Store at https://cloud.altera.com/devstore/platform/15.0.0/avdb-video-and-image-processing-design-example/.

4K video

4K Video and Image Processing

4 minutes

Hear about the challenges that 4K video processing brings, and how the Intel FPGA Video and Image Processing Suite solves these challenges.

UDX10 4K60 Video Processing Reference Design

4 minutes

This video shows a demonstration of up/down/cross conversion 4K60 UHD (RGB 4:4:4 10b) reference design with HDMI 2.0 running on Intel Arria® 10 FPGA.

Building Video Systems (ODSP1117)

19 minutes

This training introduces the different elements of the Intel FPGA video framework by showing you how to build a typical video signal chain with the Quartus II software v13.1. You will learn about the suite of video processing functions such as scalers and deinterlacers as well as reference designs, which can be used as a starting point to speed up the development. You will also learn about the development boards and kits available for rapid design prototyping.

Implementing Video Systems (ODSP1118)

70 minutes

This training introduces the Intel FPGA video platform and design flow. The course highlights various design considerations and debugging techniques, as well as discuss the algorithmic constraints of video and image processing IP. 

Streamline Video

Streamline Your Video Processing Apps with Design Examples on the VEEK

5 minutes

This video demonstrates a number of video and image processing functions based on the Intel FPGA Video and Image Processing Suite. The demonstration uses the Video & Embedded Evaluation Kit (VEEK) provided by Terasic.


Video Design Framework Workshop (IDSP230)

8 hours

In this lab-based hands-on Video and Image Processing workshop, you will explore the VIP framework, learn how to master the VIP design methodology, and get hands-on direct experience via the VIP lab exercises.

The following design examples are available from Intel for FPGAs and Intel FPGA Design Solutions Network partners.

For more information, refer to the Intel FPGA Video Design Framework.

Device Support

Typical performance and utilization figures for these functions, as well as more information on Avalon Memory-Mapped (Avalon-MM) and Avalon-ST interfaces are available in the Video and Image Processing Suite User Guide (PDF).

Basics

Year IP was first released

2009

Latest version of Quartus software supported

16.0

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Clocked Video (into Clocked Video Input and out of Clocked Video Output), Avalon-ST (all other datapaths)

IP-XACT metadata

No

Verification

Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Arria II GX/GZ, Arria V, Arria 10, Cyclone IV ES/GX, Cyclone V, Intel MAX® 10, Stratix® IV, Stratix V

Industry standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

N/A

Interoperability reports available

N/A

Technical Support

For technical support on this suite of Intel FPGA IP functions, please visit the mySupport online issue tracking system.

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