FFT Intel FPGA IP Function

What's New v17.0: Support for variable sized blocks

The fast Fourier transform (FFT) Intel® FPGA IP function is a high-performance, highly parameterizable FFT processor. The FFT function implements a radix-2/4 decimation-in-frequency (DIF) FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation.

The FFT Intel FPGA IP function accepts, as input, a complex data vector of length N (in two’s complement format) and outputs the transform-domain complex vector in natural order. An accumulated block exponent is output to indicate any data scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-noise ratio. Transform direction is specifiable on a per-block basis via an input port.

The FFT Intel FPGA IP function has the following options:

  • Radix-4 and mixed radix-2/4 implementations
  • Variable transform length
  • Block floating-point architecture—maximizes internal signal dynamic range
  • Use of internal memory

The FFT Intel FPGA IP function also:

  • Is optimized to use digital signal processing (DSP) blocks and TriMatrix memory architecture
  • Uses embedded multipliers
  • Has intellectual property (IP) functional simulation models for use in Intel FPGA supported VHDL and Verilog HDL simulators

Typical expected performance and utilization figures for this Intel FPGA IP function are provided in the FFT Intel FPGA IP Function User Guide.

For technical support on this IP core, please visit mySupport. You may also search for related topics on this function in the Knowledge Center.