Interlaken Look-Aside Protocol

Figure 1. Typical Application Block Diagram

300G Interlaken Look-Aside IP Performance Interop with TE Connectivity Using Intel® Arria® 10 Device

1st Level SignalTap IP Debug Feature

Push-button Hardware Design Examples in Intel Quartus® Prime Software

Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor, with packet transfer rates from 10 Gbps to 300 Gbps and beyond. Intel's Interlaken Look-Aside intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Intel has been a part of the Interlaken Alliance since its inception in 2007, and continues to innovate with new protocol features to provide customers with robust and easy-to-implement Interlaken Look-Aside IP solutions. Intel's FPGA Interlaken Look-Aside IP cores offer a wide range of bandwidths up to 300G.

Intel and Cavium Team Up to Provide Pre-Verified Packet Classification Solution

Intel's Interlaken Look-Aside IP core on a Stratix® V FPGA with Cavium’s NEURON Search Processor provides customers a proven packet classification solution that can easily be implemented on any networking or data center platform.

To further simplify our customers’ decision making process, Intel and Cavium have generated an interoperability report which details the various interoperability modes and performance metrics that can be achieved with this complete, high-performance chipset.

Figure 2. Intel and Cavium Interlaken Look-Aside Connectivity Setup

Table 1. Intel and Cavium Connectivity System Overview

System Overview Details
Hardware Intel: Stratix V GX device (5SGXMA7)
Cavium: NEURON Search processor evaluation board (EBA-NSP)
Interlaken Look-Aside IP configuration setup 4 lanes x 10.3125 Gbps
8 lanes x 10.3125 Gbps
Results Successfully passing traffic reliably using various packet sizes.
Logical channel processing validated.
Interlaken Look-Aside IP parameters adjusted for compatibility and performance metric data gathering.

Intel FPGA Interlaken Look-Aside IP Solution

The Interlaken Look-Aside IP core includes Intel's technology-leading transceivers: physical medium attachment (PMA), physical coding sublayer (PCS), and media access control (MAC) layers. The PCS and PMA layers are hardened within the Stratix 10, Arria 10, Stratix V, and Arria V FPGAs, thereby saving customers 30 percent to 50 percent of FPGA logic resources. In addition to resource savings, the Interlaken Look-Aside IP has been through extensive simulation verification and has been proven to work on multiple internal and customer platforms. Intel continues to set up interoperability activities with leading ASSP vendors for next-generation platforms.

Intel offers off-the-shelf and customized Interlaken Look-Aside IP solutions. For more information, please contact your local sales representative.

Table 2 shows how Intel's Interlaken Look-Aside IP improves your performance and productivity.

Table 2. Performance and Productivity Improvements

Performance Productivity
Parameter tuning enables bandwidth usage improvements as high as 35% 15% IP core timing margin accelerates full design timing closure
Consistent delivery of over 700 million packets per second on multiple customer platforms and across various vertical markets* Intel FPGA IP Evaluation Mode feature allows you to test drive IP for free and without a license
Unique combination of hardened and soft IP delivers high-frequency user clocking performance (> 300 MHz) and 30% reduced logic resourcing Fully integrated Interlaken Look-Aside IP includes PMA, PCS, and MAC layers for easy FPGA IP integration

*Interlaken Look-Aside IP configuration specific

  • Data rate selection up to 12.5 Gbps
  • Multi-lane configuration up to 24 lanes
  • Packet mode support
  • Low-latency transmit and receive datapaths
  • BurstShort support: 8 bytes or higher
  • Up to 2 logical channels
  • In-band flow control
  • Fully integrated IP (MAC, PCS, and PMA layers)
  • Tunable pre-emphasis and equalization settings
  • Custom IP deliveries available to optimize for various application needs

Table 3. Interlaken Look-Aside IP Quality Metrics


Year IP was first released


Latest version of Quartus software supported



Customization Request1


Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- IntelFPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file
Y for all, except for support of ModelSim - Intel FPGA Edition

Any additional customer deliverables provided with IP

Testbench and Design Examples

Parameterization GUI allowing end user to configure IP


IP core is enabled for the Intel FPGA IP Evaluation Mode Support


Source language


Testbench language


Software drivers provided


Driver operating system (OS) support



User interface

Avalon® Memory-Mapped

IP-XACT metadata



Simulators supported

NCSim, ModelSim, VCS/VCSMX

Hardware validated

Y, Arria 10 Transceiver Signal Integrity Development Kit

Industry standard compliance testing performed


If Yes, which test(s)?


If Yes, on which Intel FPGA device(s)?


If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)

Stratix V

Interoperability reports available

Y, Cavium NEURON Search Processor

  1. Please contact your local sales representative

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