JEDEC JESD204 is an industry standard for the interconnection of digital-to-analog and analog-to-digital converters to digital ICs and FPGAs. The first revision of the JESD204 2006 specification brought the advantages of SERDES-based high-speed serial interfaces to data converters, but it supports only a single lane with a single link with a maximum bandwidth of 3.125 Gbps. In 2008, JESD204A was released adding multiple data lanes with lane synchronization, which is key to quadrature (I/Q) sampling systems, used in 3G, 3G+, and 4G broadband wireless communications. In 2011, JESD204B [JESD204B.01] was introduced supporting 8B/10B encoding, pre-emphasis, and equalization. The JESD204B also features a higher maximum lane rate (higher bandwidth), support for deterministic latency, and support for harmonic frame clocking.
IPC-JESD204-B controller in its receiver and transmitter modules is implemented in register transfer level (RTL) VHDL-93 language according to the JEDEC JESD204B.01 standard.
Applications and Benefits
The applications for JESD204B intellectual property (IP) are related to digital signal processing (DSP) required for radar, medical imaging, wireless and cellular, military, and aerospace. The JESD204B features a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes that make board designs much easier and offers lower overall system cost. The standard is also easily scalable so it can be adapted to meet future needs. From an application point of view, the receiver and transmitter are totally separate modules – a project may utilize only one or several instances of each.
The IPC-JESD204-B offers the following competitive advantages:
- Support of rates up to 12.5 Gbps*
- 32 bits internal data processing with clock frequency 1/40 of baud rate in use enable usage in low-end and mid-end FPGAs
- MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes)
- Disabling of features mandatory to a class MCDA-ML module, if connected to a device pertaining to a class that does not support these features (JESD204 standard).
- Includes transport layer implementation with run-time programmable configuration for key parameters
- L, M, F, N, HD, SCR, CS
- Support for deterministic latency (subclass 1)
- Support for backward compatibility to JESD204A (subclass 0)
- Insertion of tail bits are performed based on register settings. Both constant and low DC content tail bits are supported.
- Support for built in test modes
- Support for error handling
- Includes 8b10b coding block
- Separate CPU interface for control and monitoring
* Maximum rates on FPGA depends on actual family speed grade respectively
MTI Radiocomp’s IP core is supported on the following device families:
- Stratix® V FPGAs
- Arria® V FPGAs
- Cyclone® V FPGAs
Request a license to evaluate this IP from MTI.
For more information on JESD204B, visit Intel’s JESD204B resource center.