Backplane Ethernet 10GBASE-KR PHY MegaCore® Function

From Intel (formerly Altera)

Figure 1. 10GBASE-KR Ethernet PHY Block Diagram

Figure 1. 10-Gigabit Ethernet MAC with 10GBASE-R PHY and serial 10-Gbps XFI or SFI interface Block Diagram

The Backplane Ethernet 10GBASE-KR PHY MegaCore® function is a transceiver PHY which allows you to instantiate both the hard standard physical coding sublayer (PCS) and the higher performance hard 10G PCS and hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE Std 802.3ap-2007 Standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multi-channel designs by instantiating more than one instance of the core.

  • Integrated 1000BASE-KX / 10GBASE-KR (1G/10Gb) backplane Ethernet PCS and PMA
  • Direct internal interface with Intel FPGA 1G/10GbE media access controller (MAC) for a complete single-chip solution
  • 10GBASE-KR auto-negotiation for negotiating between 1000BASE-KX (1 Gbps Ethernet or 1GbE) and 10GBASE-KR (10 Gbps Ethernet or 10GbE) PHY types per clause 73 of the IEEE 802.3ap-2007 standard
  • Link training to automatically configure the remote link partner transmitter PMD for the lowest bit error rate (BER) per clause 72 of IEEE 802.3ap-2007 standard
  • Forward error correction (FEC) to minimize retransmission in accordance to IEEE 802.3 and 802.3ba clause 74
  • Internal programmable algorithm for the receiver adaptation process per IEEE 8023.ap clause 72.6.10.2.3 for ease of use
  • Flexible intellectual property (IP) user controls for performance optimization in various system configurations and channels
  • Receiver-link fault status detection
  • Local serial loop-back from transmitter to receiver at the serial transceiver for self test
  • High-performance internal system interfaces
    • GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer
    • Intel FPGA Avalon® Memory-Mapped (Avalon-MM) 32 bit interface for slave management

Supported Devices

Typical expected performance and resource utilization figures for this IP core are provided in the Transceiver PHY IP Core User Guide (PDF).

Basics

Year IP was first released

2012

Latest version of Quartus® software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Any additional customer deliverables provided with IP

 

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for OpenCore Plus Support

Y

Source language

Verilog

Testbench language

 

Software drivers provided

N

Driver OS Support

 

Implementation

User interface

 GMII and SGMII

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence

Hardware validated

Arria 10

Industry standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

N

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