XAUI PHY MegaCore® Function

From Intel (formerly Altera)

As the leading provider of 10 Gbps Ethernet (10GbE) for FPGAs, Intel offers the XAUI PHY MegaCore® function intellectual property (IP) core for you to easily build systems with a very high throughput Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Intel FPGA device to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.

You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel® 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.  

  • Complete 10G Ethernet (XAUI) PHY solution for 4X 3.125 Gbps serial external interface
  • PHY consisting of 10GBASE-X physical coding sublayer (PCS), physical medium attachment (PMA), XGMII Extender Sublayer (XGXS), 10G Ethernet (XAUI), and PHY management functions
  • Direct interface with Intel FPGA 10GbE MAC for a complete solution
  • Direct standard XAUI PHY (4X 3.125 Gbps) connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, backplane, and short cable applications
  • PHY integrated into hard silicon in Intel devices with serial transceivers above 3 Gbps; also soft XAUI PCS available in Stratix® IV, Stratix V, and Arria® V FPGAs with serial transceivers
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various XAUI channel characteristics and devices in systems during operation
  • Implementing the Ethernet-standard XAUI PHY functions: data and control bits 8b/10b encoding/decoding and per-lane synchronization, data serialization/deserialization (SERDES) to and from 4X 3.125 Gbps line, receiver four-data lane alignment, deskew, and alignment of four lanes, and receiver rate matching for clock frequency compensation
  • Local serial loopback from transmitter to receiver at the device's serial transceiver for self testing
  • High-performance internal system interfaces

Soft XAUI PHY support is in the GX or GT variants of the following FPGA famlies:

In addition to soft XAUI support, the following FPGA families support a hard XAUI PHY implementation:

Typical expected performance and resource utilization figures for this IP core are provided in the Altera Transceiver PHY IP Core User Guide (PDF).

  • Complete 10G Ethernet (XAUI) PHY solution available to start your design quickly
    • Register transfer lever (RTL) and post-fit functional simulation for Intel FPGA supported Verilog HDL and VHDL simulators
    • Verification testbench and design example
    • Development boards
  • Configuration and generation via GUI-based parameter editor

For technical support on this IP core, visit mySupport online issue tracking system. You may also search for related topics on this function in the Solutions Database. For IP release notes of this and other Intel FPGA IP cores, see MegaCore IP Library Release Notes and Errata.