Intel® FPGA IP for 10G Ethernet MAC Function

The Low Latency Intel® FPGA IP for 10G Ethernet MAC offers low roundtrip latency and an efficient resource footprint. The IP offers the programmabiliyt of the various features listed below. This IP can be used in conjunction with the new Multi-Rate PHY to support the range of 1G to 10Gb data rates.

The legacy  Intel FPGA IP for 10G Ethernet MAC continues to be offered with a full feature set as noted below for applications targeting Stratix® V FPGAs and prior FPGA families.

  • Interfaces directly to external devices or optical modules with the Intel integrated standard XAUI PHY (4 x 3.125 Gbps), 10GBASE-R PHY (10.3125 Gbps), 10GBASE-KR PHY, SGMII / 1000BASE-X / 10GBASE-R PHY, or XGMII (32 x 312.5 Mbps)
  • Deficit idle count (DIC)
  • Local and remote fault signaling
  • Automatic Ethernet flow control
  • Programmable maximum receiving frame length up to 16 KB including jumbo frames
  • Promiscuous (transparent) and non-promiscuous (filtered) operation modes
  • Programmable MAC addresses and receive packet filtering based on MAC addresses
  • Programmable received frame filtering with cyclic redundancy check (CRC), length check, or oversized frame error
  • 1G-10GbE multi-speed option with run-time user data rate selection
  • IEEE 1588 v2 high-accuracy and high-precision time stamping option in hardware IP
    • 1-step and 2-step time sync
    • Supports IEEE 1588 v2 PTP packet encapsulation in IPv4, IPv6, and Ethernet
    • Real time of day clock generator (TOD) IP in design example
  • Support for virtual LAN (VLAN) and stacked VLAN tagged frames according to the IEEE 802.1Q and 802.1ad (Q-in-Q) standards, respectively
  • Statistics counters for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
  • High-performance internal system interfaces
  • Complete design examples

Low Latency 10G Ethernet MAC Intel FPGA IP is supported on the following FPGA families:

The legacy 10G Ethernet MAC Intel FPGA IP is supported on the following FPGA families:

Typical expected resource utilization and performance figures for this IP core are provided in the 10 Gbps Ethernet MAC IP User Guide (PDF) and Low Latency 10 Gbps Ethernet MAC IP User Guide (PDF).

Basics

Low Latency

Year IP was first released

2012

2013

Latest version of Intel Quartus® Prime software supported

17.1

17.1

Status

Production

Production

Deliverables

Low Latency

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

 

Y

 

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

 

Y

 

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

Low Latency

User interface

Avalon®-ST (Datapath), Avalon-MM (Management)

Avalon-ST(Datapath),

Avalon-MM(Management)

IP-XACT metadata

N

N

Verification

Low Latency

Simulators supported

Mentor Graphics*,

Synopsys*, 

Cadence*

Mentor Graphics,

Synopsys

Cadence

Hardware validated

Stratix V

Arria 10

Industry-standard compliance testing performed

UNH IEEE 802.3 compliance

UNH IEEE 802.3 compliance

If Yes, which test(s)?

Clause 4, 46, 31 and 49

Clause 4, 46, 31 and 49

If Yes, on which Intel FPGA device(s)?

Stratix V

Stratix V

If Yes, date performed

2011

2015

If No, is it planned?

 

 

Interoperability

Low Latency

IP has undergone interoperability testing

Y

N

If yes, on which Intel FPGA device(s)

Stratix V

 

Interoperability reports available

Y

 

For technical support on this IP core, please visit mySupport. You can also search for related topics on this function in the Knowledge Center. For IP release notes of this and other Intel FPGA IP cores, please see Intel FPGA IP Library Release Notes and Errata.