Intel® FPGA 40G Ethernet MAC and PHY IP

Figure 1. 40G Ethernet MAC and PHY Function in an Intel FPGA Device

Intel offers two 40 Gbps Ethernet (40GbE) Intel® FPGA IP function for systems requiring very high throughput Ethernet connectivity. The IEEE 802.3ba-2010 40 Gbps Ethernet standard compliant media access control (MAC) and PHY (PCS+PMA) enables an Intel FPGA device to interface to another device, a copper or optical transceiver module. Both of Intel FPGA's 40GbE IPs support IEEE 1588 v2 with two-step timestamping as well as backplane capability on a variety of Stratix® or Arria® FPGAs.

The Figure 1 illustrates an example of the Intel FPGA 40GbE MAC with an XLAUI interface in an Intel FPGA device. 

  • Compliant with the IEEE 802.3ba-2010 40 Gbps Ethernet standard
  • XLAUI physical medium attachment (PMA) hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125Gbps 
  • 40GbE physical coding sublayer (PCS) soft IP implemented in FPGA fabric
  • 40GbE MAC soft IP with configurable feature set
  • Supported options:
    • 40GbE 
    • MAC+PHY, PHY-only or MAC-only
    • Transmitter plus receiver (full-duplex), transmitter-only or receiver-only
    • Hardware verified to support full 40 Gbps wire speed traffic 
  • PCS bit error rate (BER) monitor
  • Programmable PCS test pattern generator and checker
  • Deficit idle count (DIC)
  • Automatic Ethernet flow control
  • Programmable MAC transmitter (TX) cyclic redundancy check (CRC) insertion and receiver (RX) CRC removal
  • Programmable maximum receive frame length up to 9,600 bytes
  • Programmable MAC address and receiver (RX) packet filtering based on MAC address
  • Promiscuous (transparent) and non-promiscuous (filtered) MAC operation modes
    • Programmable MAC received frame filtering with CRC, oversized and undersized frame error
    • Receive filtering of control frames (pause control and/or non-pause control)
  • Receive user-controllable pad removal
  • Transmit automatic pad insertion
  • Statistics status output signals for external statistics counters implementation
  • Optional 64 bit statistics counters module for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
  • Programmable link fault signalling
  • Optional preamble pass through
  • Avalon® Streaming (Avalon-ST) interface for MAC data path to client application with the start of packet (SOP) in 64 bit lane 0's most significant byte (MSB) when adapter option is used (256 bits at 312.5+ MHz)
    • Custom streaming interface with SOP possible on any 64 bit lane MSB when adapter option is not used
  • Avalon Memory Mapped (Avalon-MM) 32-bit interface for control and monitoring of MAC, PCS, PMA, and external optical module
  • Management data input/output (MDIO) or 2-wire serial interfaces for managing different optical modules
  • Passed functional and performance tests with 40/100Gb Ethernet test equipment

Basics

Low Latency

Year IP was first released

2011

2014                                 

Latest version of Intel Quartus® Prime software supported

17.0 17.0

Status

Production

Production

Deliverables

Low Latency

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

Y Y

IP is enabled for Intel FPGA IP Evaluation Mode Support

Y Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

Low Latency

User interface

Avalon-ST (Datapath), Avalon-MM (Management)

Avalon-ST

(Datapath),

Avalon-MM

(Management)

IP-XACT metadata

N

N

Verification

Low Latency

Simulators supported

Mentor Graphics*,

Synopsys*, 

Cadence*

Mentor Graphics,

Synopsys,

Cadence

Hardware validated

Arria 10

Arria 10, Stratix 10

Industry standard compliance testing performed

N

N

If Yes, which test(s)?

 

 

If Yes, on which Intel FPGA device(s)?

 

 

If Yes, date performed

   

If No, is it planned?

N

Y

Interoperability

Low Latency

IP has undergone interoperability testing

N

N

If yes, on which Intel FPGA device(s)

 

 

Interoperability reports available

N

N

For technical support on this IP, visit mySupport online issue tracking system. You may also search for related topics on this function in the Solutions Database. For IP release notes of this and other Intel FPGA IPs, see Intel FPGA IP Library Release Notes and Errata.