Intel® FPGA IP for 50G Ethernet MAC and PHY Function

With the ever-increasing usage of network data due to millions of new connected devices to servers/storages data centers, Intel offers a 50G Ethernet intellectual property (IP) solution that can be scale down to two 25GE links for flexibility, scalibilty, cost-efficient way for adapting to future network growth.

The Intel FPGA 50 Gbps Ethernet (50GbE) IP implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 50 Gbps Ethernet IP is a 128 bit Avalon-ST interface.

50G Ethernet features

  • Compliant with the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium.
  • Supports 64B/66B encoding with data striping and alignment markers to align data.
  • Avalon Memory-Mapped (Avalon-MM) management interface to access the IP control and status registers
  • Avalon Streaming (Avalon-ST) datapath interface connects to client logic with the start of frame in the most significant byte (MSB).
  • Support for jumbo packets, defined as packets greater than 1,500 bytes.
  • Receiver (RX) cyclic redundancy check (CRC) removal and pass-through control.
  • Transmitter (TX) CRC generation and insertion.
  • RX CRC checking and error reporting.
  • TX error insertion capability.
  • RX and TX preamble pass-through option for applications that require proprietary user management
  • information transfer.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Hardware and software reset control.
  • MAC provides cut-through frame processing, no store-and-forward capability.
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
  • Optional fault signalin: detects and reports local fault and generates remote fault, with IEEE
  • 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
  • Optional access to Intel FPGA Debug Master Endpoint.
  • Partial reconfiguration of the FPGA fabric.
  • Ready latency of 0 or 3 cycles for Avalon-ST TX interface.


Year IP was first released


Latest version of Intel Quartus® software supported



Early Access

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file


Any additional customer deliverables provided with IP


Parameterization GUI allowing end user to configure IP


IP is enabled for Intel FPGA IP Evaluation Mode Support


Source language


Testbench language


Software drivers provided


Driver operating system (OS) support



User interface

Avalon®-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata



Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria® 10 GT device

Industry standard compliance testing performed


If Yes, which test(s)?


If Yes, on which Intel FPGA device(s)?


If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)

Arria 10 GT device

Interoperability reports available


  • User Guide
  • Complete 50G Ethernet examples to start your design quickly
    • Dynamically generated hardware design examples within Quartus Prime software to easily test your custom configuration
    • For Arria 10 FPGAs: 50G Ethernet Design Example User Guide (PDF)
    • For Stratix 10 FPGAs: Low latency 50GE/100GE Hard-IP Ethernet Design Example User Guide