DisplayPort IP Core

DisplayPort IP Core Connection Diagram

DisplayPort is a high-speed serial interface standard for video and audio supported by industry leaders in broadcast, consumer, medical, and military applications. It is primarily used to connect video sources to display devices like computer monitors.

The DisplayPort IP core has the following advantages:

  • Higher bandwidth
  • Royalty-free standard
  • Data transmission on all four lanes
  • Latching cable to physically secure connection
  • Multi-Stream Transport to run multiple monitors from a single cable

The Intel® FPGA VESA-certified DisplayPort IP Core implements a receiver and transmitter per lane with 1, 2, or 4 differential data lanes at 1.62, 2.7, or 5.4 Gbps. High-bandwidth Digital Content Protection (HDCP)-encrypted transmission can also be integrated into our intellectual property (IP) through one of Intel's partners. For more information, contact Bitec.

IP Core Feature

Description

Scalable main data link

  • 1, 2 or 4 lane operation
  • 1.62, 2.7 or 5.4 Gbps per lane with an embedded clock

Color support

  • RGB 18, 24, 30, 36 or 48 bits per pixel (bpp) color depths
  • YCbCr 4:4:4 24, 30, 36 or 48 bpp color depths
  • YCbCr 4:2:2 16, 20, 24 or 32 bpp color depths

Transceiver data interface

40 bit (quad symbol) or 20 bit (dual symbol)

Pixels per clock

1, 2 or 4 pixels per clock

Audio

2 or 8 channels of embedded audio

Multistream transfer

1 to 4 source and sink video streams

FPGA

20 bit mode

Maximum Link Rate

40 bit mode

Maximum Link Rate

Version

Cyclone® V

2.7 Gbps

2.7 Gbps

v1.1

Arria® V GX

2.7 Gbps

5.4 Gbps

v1.2a

Arria V GZ

5.4 Gbps

5.4 Gbps

v1.2a

Stratix® V

5.4 Gbps

5.4 Gbps

v1.2a

Intel Arria 10

Not supported

5.4 Gbps

v1.2a

Basics

Year IP was first released

2012

Latest version of Intel Quartus® software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim®- Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for the Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Other (Video Data)

IP-XACT metadata

No

Verification

Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Arria 10, Arria V GX, Arria V GZ, Cyclone V, Stratix V

Industry standard compliance testing performed

Yes

If Yes, which test(s)?

VESA DisplayPort Link Layer CTS

If Yes, on which Intel FPGA device(s)?

Arria V, Arria 10

If Yes, date performed

2015-2016

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Arria V, Stratix V, Arria 10, Cyclone V

Interoperability reports available

Contact Sales

Development Kits

The following development kits and daughtercards are available from Intel and Intel partners for you to get started on your DisplayPort designs. 

Design Examples

The following design examples are available for you to run on the development kits. Their block diagrams are shown below.

Quartus Hardware Demonstration Block Diagram
UHD Scaler and Mixer Design Example

Additional support for this IP Core is available in the mySupport online issue tracking system or refer to the following documentation: