Intel® FPGA IP for Triple-Speed Ethernet

Figure 1. Triple-Speed Ethernet Function in an Intel FPGA Device

Intel® FPGA IP for Triple-speed Ethernet consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) IP. This IP function enables Intel FPGAs to interface to an external Ethernet PHY device, which, in turn, interfaces to the Ethernet network.

This IP is offered in MAC-only mode or in MAC+PHY mode. In the MAC only mode, the IP uses an external PHY chip to do signaling. Two interfaces to the external PHYs are supported: GMII (8-bit interface at 125 MHz SDR) or RGMII (4-bit interface at 125 MHz DDR). In the MAC+PHY mode, the PHY is realized using onchip transceivers or LVDS I/O with dynamic phase alignment (DPA) logic that can operate upto 1.25Gbps. SGMII or 1000Base-X protocol is used in this case. The usage of LVDS I/Os enables very scalable multi-port gigabit Ethernet (GbE) system designs while saving the serial transceivers for higher performance protocols. 

Figure 1 shows the Intel FPGA Triple-Speed Ethernet IP in an Intel FPGA device with a serial transceiver or with LVDS I/Os with DPA. The physical medium attachment (PMA) in the embedded serial transceivers is compliant to the IEEE 1000BASE-X PMA standard and compatible with SGMII specification. The PMA can alternatively be implemented using LVDS I/O with DPA for realizing a SGMII interface.

  • Complete 10/100/1000 Mbps Ethernet IP with all the necessary IP modules
    • 10/100/1000 Mbps MAC, PCS, and PMA
  • Flexible IP options
    • MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA
    • Many options for various applications and sizes as small as 900 logic elements (small-MAC)
    • Standard-based statistics counters supporting simple network management protocol (SNMP) Management Information Base (MIB and MIB-II) and Remote Network Monitoring (RMON)
    • Parameterizable FIFO or FIFO-less MAC options
    • IEEE 1588 v2 high accuracy and high precision time stamping option in hardware IP
      • 1-step and 2-step time sync
      • Supports IEEE 1588 v2 PTP packet encapsulation in IPv4, IPv6 and Ethernet
      • Real time of day clock generator (ToD) IP in design example
  • Many external Ethernet interface options for various Intel FPGA device families
    • MII (10/100 Mbps), GMII, RGMII, and SGMII (10/100/1000 Mbps), 1000BASE-X, and TBI (1 Gbps)
    • Management data I/O (MDIO) for external PHY device management

Basics

1588 v2 option

Year IP was first released

2007

2012

Latest version of Intel Quartus® Prime software supported

17.1

17.1

Status

Production

Production

Deliverables

1588 v2 option

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

Y Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

1588 v2 option

User interface

MII (10/100 Mb) GMII or RGMII (1000 Mbps)

MII (10/100 Mb) GMII or RGMII (1000 Mbps)

IP-XACT metadata

N

N

Verification

1588 v2 option

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Mentor Graphics, Synopsys, Cadence

Hardware validated

Arria 10

Arria 10

Industry standard compliance testing performed

UNH IEEE 802.3 compliance  

UNH IEEE 802.3 for MAC/PH , N/A for 1588 option.   

If Yes, which test(s)?

Clause 4, 46, 31 and 49

Clause 4, 46, 31, and 49

If Yes, on which Intel FPGA device(s)?

Intel Arria 10

Intel Arria 10

If Yes, date performed

2011

2012

If No, is it planned?

 

 

Interoperability

1588 v2 option

IP has undergone interoperability testing

N

N

If yes, on which Intel FPGA device(s)

 

 

Interoperability reports available

N

N

For technical support on the Triple-Speed Ethernet Intel FPGA IP function, please visit the Triple-Speed Ethernet IP Core Resource Center. Additional support for Intel FPGA IP functions is available in the mySupport online issue tracking system. You may also search the Knowledge Base for topics related to this function.