HDMI IP Core Connection Diagram

The Intel FPGA High-Definition Multimedia Interface (HDMI) compliant intellectual property (IP) core provides support for the next generation of video display interface technology. Due to its ability to send high-definition audio and video, HDMI has become the most common digital connection in consumer electronics.

The HDMI cable and connectors carry four differential pairs that are composed of three data channels and one clock channel.  You can use these channels to carry video, audio, and auxiliary data at a raw bit rate of up to 3.4 Gbps or 6 Gbps per channel. HDCP-encrypted transmission can also be integrated into our IP through one of Intel’s partners. Contact Bitec for more information.

HDMI 2.0 Demonstration

The following video demonstrates 4Kp60 resolution display using our HDMI IP Core on the Stratix® V GX Development Kit.

IP Core Feature


Color support

  • 8, 10, 12 or 16 bits per color (bpc)
  • RGB and YCbCr 444, 422 and 420 color modes

Symbols per clock

1, 2, or 4 symbols per clock


2 or 8 channels of embedded audio

FPGA Device Family

One Symbol per Clock

Maximum Data Rate

Two Symbols per Clock

Maximum Data Rate

Four Symbols per Clock

Maximum Data Rate

HDMI Version

Arria® V

1,875 Mbps

3,276.8 Mbps

5,940 Mbps

v1.4 and v2.0

Cyclone 10 

Not supported

5,940 Mbps

Not supported

v.1.4 and v2.0

Stratix V

5,800 Mbps

5,940 Mbps

Not supported

v1.4 and v2.0

Arria 10

Not supported

5,940 Mbps

Not supported

v.1.4 and v2.0


Year IP was first released


Latest version of Intel® Quartus® software supported





Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP


Parameterization GUI allowing end user to configure IP


IP core is enabled for Intel FPGA IP Evaluation Mode Support


Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided


Driver operating system (OS) support



User interface

Other (Video Data)

IP-XACT metadata



Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Arria 10, Arria V, Stratix V

Industry standard compliance testing performed


If Yes, which test(s)?

HDMI Source/Sink Compliance Test CTS 1.4b

If Yes, on which Intel FPGA device(s)?

Arria V

If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)

Arria V, Stratix V, Arria 10

Interoperability reports available

Contact Sales

Development Kits

The following development kits are available from Intel and Intel partners for you to get started on your designs.

FPGA Board

On-board HDMI Interface

BITEC Daughtercard

Arria 10 GX Development Kit

Transmit (TX) only

FPGA mezzanine card (FMC) daughtercard

TX and receive (RX)

Arria V GX Development Kit

TX only

High-speed mezzanine card (HSMC) daughtercard

TX and RX

Stratix V GX Development Kit


Design Examples

The following design example is available for you to run on the development kits. The block diagram is shown below.

Quartus Hardware Demonstration Block Diagram
Arria 10 UHD Video Reference Design Block Diagram

Additional support for this Intel FPGA IP function is available in the mySupport online issue tracking system.