Interlaken Protocol

From Intel (formerly Altera)

Figure 1. Typical Application Block Diagram

1st Level SignalTap™ IP Debug Feature

Push-button Hardware Design Examples in Quartus® Prime Software

Interlaken is a scalable protocol that enables chip-to-chip packet transfers at rates from 10 Gbps to 300 Gbps and beyond. Intel® FPGA's Interlaken intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Intel entered the market with 10G Interlaken IP cores and now offers up to 300G Interlaken IP cores.

Brocade Integrates and Qualifies Intel's FPGA 120G and 150G Interlaken IP

“Intel's FPGA Interlaken IP delivers the bandwidth scalability and data efficiency our customers require not only for big data, but also for other applications that require high-rate data transfers through the network.”

Majid Afshar, Vice President of ASIC and Hardware Engineering, Brocade

Intel's FPGA Interlaken IP provided Brocade a favorable IP strategy enabling them to simply reconfigure the IP for their various line module configurations. This uniqueness enables Brocade to offer their customers the options to choose the right level of services given certain budget constraints. The combination of Intel's FPGA Interlaken IP core in the Stratix® V FPGA with Brocade's router innovations eliminates the bottlenecks to scale cloud-optimized networks. This allows businesses to manage high volumes of big data and other applications that require high-rate data transfers through the network.

Intel's FPGA Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet, and data center applications that demand high IP configurability to optimize for system performance and scalability.

Figure 2 shows Brocade's line card module integrated with Intel's FPGA Interlaken IP in the Stratix V FPGA.

Figure 2. Brocade MLX Series Multi-Terabit Router with Interlaken IP and Stratix V FPGA

Intel's FPGA Interlaken IP Solution

The Interlaken IP core includes Intel’s technology-leading transceivers: physical medium attachment (PMA), physical coding sublayer (PCS), and media access control (MAC) layers. The PCS and PMA layers are hardened within the Stratix 10, Arria® 10, Stratix V, and Arria V FPGAs, thereby saving customers 30 percent to 50 percent of FPGA logic resources. In addition to resource savings, the Interlaken IP has been through extensive simulation verification and has been proven to work on multiple internal and customer platforms. Intel's FPGA Interlaken IP solution has passed the Interlaken Alliance's device interoperability tests. Intel continues to set up interoperability activities with leading ASSP vendors for next-generation platforms.

Intel offers both MegaCore® function-based and customized Interlaken IP solutions. For more information, please contact your local Intel FPGA sales representative or email interlaken@altera.com.

Table 1 shows how Intel FPGA Interlaken IP improves your performance and productivity.

Table 1. Performance and Productivity You Can Expect

Performance Productivity
Parameter tuning enables bandwidth usage improvements as high as 35% 15% IP core timing margin accelerates full design timing closure
Consistent delivery of over 150 million packets / second on multiple customer platforms and across various vertical markets† OpenCore Plus feature allows you to test drive IP for free and without a license
Unique combination of hardened and soft IP delivers high-frequency user clocking performance (> 300 MHz) and 30% reduced logic resourcing Fully integrated Interlaken IP includes MAC, PCS, and PMA layers for easy FPGA IP integration
Notes:

†Interlaken configuration specific

  • Data rate selection up to 12.5 Gbps
  • Multi-lane configuration up to 24 lanes
  • Interleave (segment) mode and packet mode support
  • Enhanced scheduling
  • Multi-segment or Start-of-Packet (SOP) alignment user interface options
  • I/O controllable Burst settings (Min, Max, Short) 
  • Programmable Meta Frame lengths
  • Up to 256 logical channels
  • Multiple-use field access
  • In-band and out-of-band flow control (calendar page options)
  • Advanced error handling and error injection capabilities
  • Retransmission
  • Fully integrated IP (MAC, PCS, and PMA layers)
  • Tunable pre-emphasis and equalization settings
  • Custom IP deliveries available to optimize for various application needs

Intel's FPGA Interlaken IP core is supported on the following device families:

Table 2. Interlaken IP Quality Metrics

Basics

Year IP was first released

2012

Latest version of Quartus software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim* - Intel® FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file
Y for all, except for providing Readme file and support for ModelSim- Intel FPGA Edition

Any additional customer deliverables provided with IP

Testbench and Design Examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for OpenCore Plus Support

Y

Source language

Verilog and VHDL

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon® Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS/VCSMX

Hardware validated

Y, Arria 10 Transceiver Signal Integrity Development Kit

Industry standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Stratix V

Interoperability reports available

Y, Broadcom ARAD and Cavium OCTEON II

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