Intel® FPGA IP for 100GE MAC and PHY Function

Figure 1. 100G Ethernet Intel FPGA IP Function

Intel offers ultimate flexibilty, scalability, and configurability with the Intel® FPGA IP for 100G Ethernet function targeted to network infrastructure and data centers. The 100G Ethernet Intel FPGA IP function is IEEE 802.3ba-2010 (PDF) standard compliant and includes a media access control (MAC), PHY, comprised of physical coding sublayer (PCS) and physical medium attachment (PMA), an optional forward error correction (FEC) block, timestamping with IEEE 1588v2 support and the capability to drive backplanes on supported Stratix® and Arria® FPGAs. This IP can be used for chip-to-chip interconnect or to interface to copper or optical transceiver modules. 

  • Compliant with the IEEE 802.3ba-2010 (PDF) 100 Gbps Ethernet standard
  • CAUI and CAUI-4 PMA hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125 Gbps or 25.78125 Gbps
  • 100GbE physical coding sublayer (PCS) and MAC soft IP cores implemented in FPGA fabric
  • Supported options
    • Ultra low latency variant
    • MAC+PHY, PHY-only or MAC-only
    • Transmitter plus receiver (full-duplex), transmitter-only or receiver-only
    • 100GbE PHY options: CAUI (10 x 10.3125 Gbps) or CAUI-4 (4 x 25.78125 Gbps)
  • Supports full 100 Gbps wire speed traffic
  • PCS bit error rate (BER) monitor
  • Programmable PCS test pattern generator and checker
  • Deficit idle count (DIC)
  • Automatic Ethernet flow control
  • Programmable MAC transmitter (TX) cyclic redundancy check (CRC) insertion and receiver (RX) CRC removal
  • Programmable maximum receive frame length up to 9,600 bytes
  • Programmable MAC address and receiver (RX) packet filtering based on MAC address
  • Promiscuous (transparent) and non-promiscuous (filtered) MAC operation modes
    • Programmable MAC received frame filtering with CRC, oversized and undersized frame error
    • Receive filtering of control frames (pause control and/or non-pause control)
  • Receive user-controllable pad removal
  • Transmit automatic pad insertion
  • Statistics status output signals for external statistics counters implementation
  • Optional 64 bit statistics counters module for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
  • Programmable link fault signalling
  • Optional preamble pass through
  • Avalon® Streaming (Avalon-ST) interface for MAC datapath to client application with the start of packet (SOP) in 64 bit lane 0's most significant byte (MSB) when adapter option is used (512 bits at 312.5+ MHz)
    • Custom streaming interface with SOP possible on any 64 bit lane MSB when adapter option is not used (320 bits at 312.5+ MHz)
  • Avalon Memory Mapped (Avalon-MM) 32 bit interface for control and monitoring of MAC, PCS, PMA, and external optical module
  • Management data input/output (MDIO) or 2-wire serial interfaces for managing different optical modules
  • Passed functional and performance tests with 100Gb Ethernet test equipment

Basics

Year IP was first released

2015

Latest version of Intel Quartus® software supported

17.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

N/A

Software drivers provided

N

Driver OS Support

N/A

Implementation

User interface

Avalon-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Arria 10

Industry standard compliance testing performed

N

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

N/A

Interoperability reports available

N

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