RapidIO Intel® FPGA IP Function

  • PHY based on embedded transceivers
  • Easy to use
    • IP Parameter Editor allows easy manual optimization of parameters, such as interface FIFO depths, address translation windows, and output differential voltage and pre-emphasis
    • Easy configuration provides ways to reduce resource utilization to create smaller Intel® FPGA IP function variations depending on application needs
    • Platform Designer (formerly Qys) for system interconnect
  • Robust solution

For a system-level integration-ready solution, you can save several months of design time by selecting all RapidIO layers—including features such as address translation and simple Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) FIFO interfaces.

Protocol Solution

Figure 1 shows an example of a system built using the Platform Designer with a Nios® II soft embedded processor as a processing element. The program memory can include “boot code” for system-level enumeration of the various end points and also configure the capability address registers of the endpoints and the Intel FPGA IP function.

Figure 1. A Complete SRIO System

The RapidIO* standard was adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA) such as XAUI or CEI for up to 6.25 Gbaud data rate. Intel FPGAs are also capable of supporting RapidIO Gen3 data rates and electricals.

Intel Offers Two Distinct RapidIO Intel FPGA IP Functions

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO Intel FPGA IP function user guides.

Basics

Year IP was first released

2009

Latest version of Intel Quartus® Prime software supported

17.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon-MM, Avalon-ST

IP-XACT metadata

No

Verification

Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Intel Arria 10, Arria V, Cyclone V, Intel Stratix 10, Stratix V

Industry standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

No

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Arria V, Intel Arria10, Intel Stratix 10

Interoperability reports available

Yes

For technical support on the RapidIO Intel FPGA IP function, please visit the RapidIO Intel FPGA IP Support Center. Additional support for the Intel FPGA IP function is available in the mySupport online issue tracking system. You can also search for related topics on this function in the Knowledge Database.

A web-based technical training on configuring the RapidIO Intel FPGA IP function is also available.