Intel® FPGA JESD204B IP

Jump-Start Your JESD204B Implementation

Intel provides the JESD204B serial interface in the industry across multiple products –from low-cost or low-power to high-performance FPGAs and SoCs. With our unique implementation of a full transport layer, design engineers no longer need to analyze documentation to integrate or develop a transport layer solution. This can save weeks in logic design and verification.

Intel’s hardware interoperability testing of the Intel® FPGA Intellectual Property (IP) for JESD204B with analog-to-digital converter (ADC) and digital-to-analog converter (DAC) vendors as well as RFICs and analog front ends, including Analog Devices Incorporated (ADI) and Texas Instruments (TI) gets you to market faster.

Block Diagram

The Intel FPGA IP for JESD204B utilizes the Avalon® Streaming (Avalon-ST) source and sink interfaces with unidirectional flow of data to transmit and receive data on the FPGA fabric interface.

 

The Intel FPGA IP for JESD204B delivers the following key features:

  • Lane rates of up to 12.5 Gbps (characterized and certified to the JESD204B standard), and lane rates up to 16 Gbps (uncharacterized and not certified to the JESD204B standard)
  • Run-time reconfiguration of JESD parameters (L, M, F, S, N, K, CS, CF, data rate)
  • Base and PHY partitioning for portability
  • Subclass 0 operating mode for backward compatibility to JESD204A
  • Subclass 1 and 2 operating modes for deterministic latency support between the ADC/DAC and FPGA
  • Multi-device synchronization
  • Serial lane alignment and monitoring 
  • Ability to tune latency in IP core 
  • Transceiver channel sharing for transmitter (TX) and receiver (RX) to optimize transceiver count 
  • Hardware-validated design examples that include transport layer design 

Basics

Year IP was first released

2014

Latest version of Intel Quartus® Prime software supported

18.0

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

  • Y
  • Y
  • Y
  • Y (in user guide)
  • N

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode support

Y

Source language

Verilog and VHDL (at wrapper-level) 

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N

Implementation

User interface

Avalon®-ST (Datapath) and Avalon-MM (CSR)

IP-XACT metadata

N

Verification

Simulators supported

N/A

Hardware validated

Y, on Intel FPGA development kits

Industry-standard compliance testing performed

Y

If Yes, which test(s)?

Electrical testing

If Yes, on which Intel FPGA device(s)?

 Intel Stratix® 10,  Intel Arria® 10, Intel Cyclone® 10 GX, Arria V, and Stratix V

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Stratix 10, Intel Arria 10, Intel Cyclone 10 GX, Arria V, Stratix V

Interoperability reports available

Y

Intel® FPGA IP is supported on the following device families:

  • Intel Stratix® 10 FPGAs and SoCs 
  • Intel Arria® 10 FPGAs and SoCs
  • Intel Cyclone® 10 GX FPGAs
  • Stratix V FPGAs
  • Arria V FPGAs and SoCs
  • Cyclone V FPGAs and SoCs 

For more information on Intel FPGA IP for JESD204B, view the JESD204B IP Core User Guide

Learn more from these application notes: 

 

Intel has performed JESD204B IP hardware validation with converter devices from the following leading vendors.  Download hardware checkout reports listed below.  

Analog Devices  

Texas Instruments

 
Note: Texas Instruments' TSW14J57 and TSW14J56 evaluation modules (EVMs) are designed using Intel Arria 10 FPGA and Arria V FPGA respectively. All devices from Texas Instruments supported by the TSW14J57EVM and the TSW14J56EVM have been hardware validated to be compatible with the Intel FPGA IP for JESD204B.  

For technical support on this IP core, please visit mySupport. You may also search for related topics on this function in the Knowledge Center.

Interested in evaluating the Intel® FPGA IP for JESD204B quickly? Trying to reduce development time of your JESD204B system?  

Intel provides several reference designs that equip you with ready-made JESD204B solutions to interface an Intel FPGA to an ADC or DAC from leading data converter providers.  

Reference designs are available on the Other High-Speed Serial Interface - Support Center page