From Altera

 

Jump-Start Your JESD204B Implementation

Altera provides the easiest to use JESD204B serial interface in the industry across multiple products –from low-cost or low-power to high-performance FPGAs and SoCs. With our unique implementation of a full transport layer, design engineers no longer need to analyze documentation to integrate or develop a transport layer solution. This can save weeks in logic design and verification.

Altera’s hardware interoperability testing of our JESD204B MegaCore® intellectual property (IP) with analog-to-digital converter (ADC) and digital-to-analog converter (DAC) vendors as well as RFICs and analog front ends, including Analog Devices Incorporated (ADI) and Texas Instruments (TI) gets you to market faster.

 

Block Diagram

The JESD204B MegaCore IP utilizes the Avalon® Streaming (Avalon-ST) source and sink interfaces with unidirectional flow of data to transmit and receive data on the FPGA fabric interface.