Intel® FPGA IP for DDR and DDR2 SDRAM High-Performance Controller

Figure 1. DDR2 SDRAM High-Performance Controller System-Level Diagram

The Intel® FPGA intellectual property (IP) for DDR and DDR2 SDRAM High-Performance Controller provides simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The Intel FPGA IP work in conjunction with the Intel FPGA ALTMEMPHY physical interface IP. The controllers offer a half-rate interface and a full-rate interface to the customer application logic. For exact device support, please refer to the user guide.

The parameter editor generates a design example, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional delay-locked loop (DLL) (for Stratix® series FPGAs only). The design example is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

  • Flexible architecture
    • Supports industry-standard DDR/DDR2 SDRAM devices and modules
    • Creates a complete DDR/DDR2 solution by bolting onto the Intel FPGA IP for ALTMEMPHY physical interface 
  • Feature rich
    • Provides full-rate application logic interface
    • Has integrated error correction code (ECC) functionality
    • Offers optional user-controller refresh
    • Supports auto-precharge
    • Supports self-refresh and power-down modes
  • Ease of use
    • Supports Platform Designer (formerly Qsys) IP
    • Offers optional Avalon® Memory-Mapped local interface
    • Includes a parameter editor
    • Provides support for Intel FPGA IP Evaluation Mode

Typical expected performance and utilization figures for this Intel® FPGA IP function are provided in the DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide (PDF).