QDR II SRAM Controller MegaCore Function

from Intel® (formerly Altera®)

Included in IP Base Suite—FREE with Quartus® Prime Standard and Pro Edition design software


  • Support for QDR II and QDR II+ SRAMs
    • Support for burst of two and four memory type
    • Support for 8-bit, 18-bit, and 36-bit QDR II SRAM interfaces
  • Flexible and robust design
    • Support for two-times and four-times data width on the local side (four-times for burst of four only)
    • Automatic concatenation of consecutive reads and writes (narrow local bus width mode only)
    • Intellectual property (IP) functional simulation models for use in VHDL and Verilog HDL simulators supported by Intel
    • Easy-to-use IP Toolbench interface and example design
    • Support for OpenCore Plus evaluation

General Description

The QDR II SRAM Controller MegaCore® function provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules. The QDR II SRAM controller ensures that the placement and timing are in line with QDR II specifications. The QDR II SRAM controller’s local interface is compatible with the Intel FPGA Avalon® Memory-Mapped interface, for easy integration into SOPC Builder.

The QDR II SRAM Controller MegaCore functions optimized for Intel FPGA Stratix® series and Cyclone® IV FPGAs. The advanced features available in these devices allow you to interface directly to QDR II SRAM devices.

The IP Toolbench-generated example design instantiates a phase-locked loop (PLL), an optional delay-locked loop (for Stratix II FPGAs only), an example driver, and your QDR II SRAM Controller custom variation. The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. You can replace the QDR II SRAM Controller encrypted control logic in the example design with your own custom logic, which allows you to use the Intel FPGA clear-text resynchronization and pipeline logic and datapath with your own control logic.

Design Example

This design example implements an 18–bit wide, 400-MHz or 1600-Mbps memory interface on the Stratix III EP3SL150F1152C2 device. Although the design example is specifically for the QDR II+ SRAM memory interface with a Stratix III FPGA, the design flow is the same when using a QDR II SRAM for the memory interface with a Stratix IV FPGA.

IP Evaluation

Use the Intel FPGA OpenCore Plus Evaluation flow to test drive this MegaCore function.


Typical expected performance and utilization figures for this MegaCore function are provided in the QDRII SRAM Controller MegaCore Function User Guide (PDF).


Intel awards the I-Tested certification to MegaCore functions or Intel FPGA Megafunctions Partners Program (AMPPSM) IP cores that have been verified in an Intel FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.

For more information, see MegaCore Verification in the QDRII SRAM Controller MegaCore Function User Guide (PDF).

Technical Support

For technical support on this MegaCore function, please visit the mySupport online issue tracking system. You may also search for related topics on this function in the Knowledge Database.

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