Need to boost performance? No problem. Hardware acceleration is as easy as using an FPGA's programmable logic to offload and accelerate tasks that are typically implemented in application software.

Read on to learn more about accelerating software in FPGAs.

Custom Instructions

Similar to hardware accelerators, custom instructions allow Nios II designers to increase system performance by offloading portions of the software code to hardware functions. Custom instructions, however, are implemented within the processor boundary, extending the CPU instruction set to accelerate time-critical software.

The configurable nature of Nios II processors enables designers to integrate custom logic directly into the arithmetic logic unit (ALU). Custom instructions let developers optimize software inner loops for applications such as digital signal processing (DSP), packet header processing, and computationally intensive applications, reducing complex operational sequences to a single instruction implemented in hardware.

Using custom instructions, designers can optimize their system performance in a way not possible with traditional off-the-shelf processors. Altera's Qsys system integration tool provides a graphical user interface that developers can use to easily import their own hardware design files to create custom instructions that are automatically integrated into the Nios II processor.

Nios II processor custom instructions provide:

  • Up to 256 user-defined instructions
  • Fixed and variable-cycle operation
  • User-logic import wizard
  • C and assembly language software macros

Figure 2 shows the flexibility of the custom instruction logic.

Figure 2. Custom Instruction Logic

For more details, see the Nios II processor handbook.