Altera's Nios® II processors give you the ultimate flexibility to achieve the exact performance required for your embedded design, without overpaying for high clock frequency, power-hungry off-the-shelf processors. Additionally, Nios II processors help you avoid last-minute hand-tuning of assembly language code, giving you configurable performance features that can be designed in as needed.
Table 1 lists the performance features and benefits of Nios II processors.
Table 1. Nios II Performance Features and Benefits
|High-Performance Processor Core||Optimized for performance-critical applications, the Nios II/f "fast" core has a 6-stage pipeline, dynamic branch prediction, instruction and data cache, and 250+ MHz performance. High-performance FPGAs, such as those in the Stratix® III device family, give the Nios II/f core enough performance for many core processing tasks.|
|Multi-Processor Systems||Use multicore systems to scale a system's performance or to divide software applications into simpler tasks. The Nios II Embedded Design Suite (EDS) includes support for creating customized multicore systems. Nios II processors, combined with extremely high-density FPGAs such as those in the Stratix III device family, are ideal for creating high-performance multiprocessor applications.|
|High-Bandwidth Bus Structure||Automatically generate an Avalon® interconnect fabric to support any system that you build by using the SOPC Builder system generation tool, which allows you to generate high-throughput systems that support simultaneous multiple master/slave connections, direct memory access (DMA) channels, and on-chip data buffers.|
|Custom Instructions||Accelerate time-critical software algorithms by adding custom instructions to the Nios II instruction set.|
|Fast Configurable On-Chip Memory||Create fixed low-latency on-chip memory buffers for performance-critical applications.|
Flexible Processing With FPGAs
Traditionally, embedded developers have had limited options for accelerating performance near the end of a design cycle, including buying a faster processor or hand-tuning assembly language subroutines. While both options can be effective, the trade-offs they bring are too large to ignore. What designer wants to add cost or increase power usage? Who wants hand-optimized assembly code that is tied closely to a specific processor architecture?
Nios II processors are the right choice if:
Your application is too large and complex to develop and debug and still meet the schedule
- Create a multiprocessor Nios II system with a few mouse clicks and partition your code into two smaller, simpler applications. You will meet timing, validate your application, and be shipping product in no time.
Your application does not meet your timing requirements
- Nios II developers can add a custom instruction or hardware accelerator to selectively boost only the bottle-neck routine.
Altera® FPGAs and Nios II processors give you a whole new toolbox of performance features, as well as many options for reducing risk in embedded design.