The Nios® II processor architecture supports a Joint Test Action Group (JTAG) debug module that provides on-chip emulation features to control the processor remotely from a host PC. PC-based software debugging tools, such as the Nios II Embedded Design Suite (EDS), communicate with the JTAG debug module and enable designers to do the following:
- Downloading programs to memory
- Starting and stopping execution
- Setting breakpoints and watchpoints
- Analyzing registers and memory
- Collecting real-time execution trace data
The debug module connects to the JTAG circuitry built into all Altera® FPGAs (shown in Figure 1) and connects to the host PC via a download cable, such as the Altera USB BlasterTM cable (included in the Nios II development kits) or a third-party system analyzer probe.