Nios II Processor Variants

Used by more designers than any other soft processor in the world, Nios® II embedded processors remain the industry-standard processor for FPGA design. The Nios II family of embedded processors currently consists of three processor cores that implement a common instruction set architecture, each optimized for a specific price/performance point, and all supported by the same software tool chain.

Designers can choose from the following cores:

For technical detail on the Nios II processor cores, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook.

Note: The Nios II/s core is only available with the Nios II Classic product. A core with the same configuration can now be created by selecting the /f core and configuring the appropriate options. 

Nios II/f "Fast"

Altera specifically designed the Nios II/f “fast” processor for high performance. With performance over 300 MIPS* (*Dhrystones 2.1 benchmark), it is optimal for performance-critical applications as well as applications with large amounts of code and data, such as running a full-featured operating system.

The Nios II/f core is supported by the Nios II Embedded Design Suite (EDS), including the Eclipse-based Nios II Integrated Development Environment (IDE).

The Nios II/f core features:

  • Memory management unit (MMU)
  • Memory protection unit (MPU)
  • External vectored interrupt controller
  • Advanced exception support
  • Separate instruction and data caches (512 bytes to 64 KB)
  • Access to up to 4 GB of external address space
  • Optional tightly-coupled memory for instructions and data
  • Six-stage pipeline to achieve maximum MIPS* (*Dhrystones 2.1 benchmark) per MHz
  • Single-cycle hardware multiply and barrel shifter
  • Hardware divide option
  • Dynamic branch prediction
  • Up to 256 custom instructions and unlimited hardware accelerators
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

The Nios II/f core provides additional functionality and performance when targeting Altera® device families with digital signal processing (DSP) blocks. In this case, the Nios II/f core provides hardware multiply circuitry that achieves single-cycle multiply operations. The multiply unit also functions as a single-cycle barrel shifter. The Nios II/f core provides optional divide circuitry that accelerates divide operations.

For the highest performance, implement the Nios II/f core in Altera's highest performance FPGAs.

Nios II/e "Economy"

Altera specifically designed the Nios II/e "economy" processor cores to use the fewest FPGA logic and memory resources. It is now offered free (for both Nios II Classic and Nios II Gen2 processors), no license required, with the Quartus® Prime software and Quartus II software version 9.1 and later. The Nios II/e core has higher performance but is in the same cost class as a typical 8051 architecture, achieving over 30 DMIPS at up to 200 MHz, and using fewer than 700 logic elements (LEs).

The core is supported by the Nios II Embedded Design Suite (EDS), including the Eclipse-based Nios II Integrated Development Environment (IDE).

The free Nios II/e core features:

  • Up to 2 GB of external address space 
  • JTAG debug module
  • Complete processors in fewer than 700 LEs
  • Optional debug enhancements
  • Up to 256 custom instructions

The Nios II/e core is optimal for cost-sensitive applications, such as those found in the automotive, industrial, and consumer markets. This core is often paired with Altera's low-cost FPGAs.

Nios II/s "Standard"

The Nios II/s core is only available with the Nios II Classic product. A core with the same configuration can now be created by selecting the /f core and configuring the appropriate options. The Nios II/s "standard" processor core was orginally created to implement a smaller processor core without a significant trade-off in software performance. The Nios II/s core (or equivalent /f configuration) is optimal for cost-sensitive, medium-performance applications, including those with large amounts of code and/or data, such as systems running a full-featured operating system.

The core is supported by the Nios II Embedded Design Suite (EDS), including the Eclipse-based Nios II Integrated Development Environment (IDE).

The Nios II/s core features:

  • Instruction cache
  • Up to 2 GB of external address space
  • Optional tightly coupled memory for instructions
  • 5-stage pipeline
  • Static branch prediction
  • Hardware multiply, divide, and shift options
  • Up to 256 custom instructions
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

The Nios II/s core provides additional functionality and performance when targeting Altera device families with DSP blocks. In this case, the Nios II/s core provides hardware multiply circuitry that achieves 3-cycle multiplication operations. The multiply unit also functions as a barrel shifter.