Nios II Processor Feature Set and Performance

The Nios® II processor family consists of two configurable 32 bit Harvard architecture cores:

  • Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit (MMU), or memory protection unit (MPU)
  • Economy (/e core): Optimized for smallest size, and available at no cost (no license required)


Note: The Nios II Classic family also contained a Standard (/s core) that offered a balance of performance and size, the current /f core can now be configured with the same feature set as the Nios II Classic /s core. 
 

Summary of Perfomance

  • Download the latest Nios II processor performance benchmarks data sheet

 

Summary of Supported Features/Options

  • MMU
  • MPU
  • External Vector Interrupt Controller with up to 32 interrupts per controller
  • Advanced exception support
  • Separate instruction and data caches (configurable from 512 bytes to 64 KB)
  • Access to up to 4 GB of external address space
  • Optional tightly-coupled memory for instructions and data
  • Up to six-stage pipeline to achieve maximum DMIPS (Dhrystone 2.1 benchmark) per MHz
  • Single-cycle hardware multiply and barrel shifter
  • Hardware divide option
  • Dynamic branch prediction
  • Up to 256 custom instructions and unlimited hardware accelerators
  • Configurable JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
     

Industry's Most Advanced System Integration and Debug Tools

The Quartus® Prime software includes Qsys, the industry's most advanced system integration tool for processor system design. With Qsys, designers can configure and integrate processors, peripherals, memory controller, communication controllers, and custom intellectual property (IP) cores using a graphical user interface; once the design is complete the tool generates the system and connects the IP components with an automatically generated high-performance system interconnect.

Quartus Prime software system debug capabilities provide advanced debug capabilities at every level of the design:

  • Transceiver and memory tool kit for protocol and memory debugging
  • SignalTap™ II logic analyzer for signal and logic-level transactions
  • Signal probe for I/O-level transactions
  • System console for register-level transactions

 

Free Embedded Peripheral IP Cores

A rich portfolio of Qsys-ready embedded peripheral IP cores are provided at no cost, these include:

  • Direct memory access (DMA) controller
  • Scatter-gather DMA controller
  • SDR SDRAM controller
  • CFI flash controller
  • EPCS serial flash controller
  • JTAG UART controller
  • UART controller
  • Serial peripheral interface (SPI) controller
  • PIO controller
  • Mutex core
  • Mailbox core
  • Timer core
  • Vectored interrupt controller core
  • Performance counter
  • Phase-locked loop (PLL)
  • Avalon® interconnect components

 

Free Embedded Software Tools, Software, and Middleware

Everything you need to develop robust software applications is provided for you in the Nios II EDS. You'll feel right at home with the Eclipse-based Nios II Software Build Tools for Eclipse and a full range of software and operating system support provided by Intel and its partners.

The Nios II EDS includes:

  • Nios II Software Build Tools for Eclipse, a fully integrated graphical development environment
  • GNU tools (GCC compiler, GDB debugger)
  • Software examples and templates, device drivers, and bare-metal hardware abstraction layer (HAL)
  • Free Nichestack TCP/IP Network Stack, Nios II Edition, commercial grade network stack
  • Evaluation version of Micrium's popular MicroC/OS-II real-time operating system (RTOS)

 

See what's new in the latest release of Nios II EDS.

 

Find out more details on the Nios II processor: