Nios II Processor Peripherals and Interfaces

Altera Embedded Intellectual Property Suite

The Altera® Embedded Intellectual Property (IP) Suite is a value bundle of Altera's most popular embedded IP cores and software. This IP suite contains all the building blocks for your embedded design, including the Nios® II processor, a complete Ethernet solution with the Triple-Speed Ethernet MegaCore® function, DDR/DDR2/DDR3 memory controllers, 16550 UART and commercial-grade network stack. See Table 1 for details.

Table 1. Embedded IP Suite

Ordering Code Price Ordering Information
IPS-EMBEDDED $995

This IP suite includes all the IP you need to ship a standard Nios II processor design. Upgrade your kit with this perpetual use, royalty-free license bundle for embedded design.

  • Nios II Processor
  • Triple-Speed Ethernet MegaCore Function
  • DDR/DDR2/DDR3 High-Performance Memory Controllers
  • NicheStack TCP/IP Network Stack - Nios II Edition
  • 16550 UART

Standard Peripherals

The Nios II processor includes a library of commonly used peripherals and interfaces that are available for use royalty-free in Altera FPGAs. User-developed peripherals and interfaces are easily imported into the Nios II processor systems using an import wizard that provides an easy method for design reuse.

Ready-to-use design blocks are delivered in both Verilog HDL and VHDL source code and include all the necessary software routines for easy system integration. Table 2 lists the peripherals and interfaces included with the Nios II processor. More SOPC Builder-ready IP cores are available on the IP MegaStore™ website.

Table 2. Nios II Peripherals and Interfaces

Peripheral Description Documentation
JTAG UART Communicates serial character streams between a host PC and an SOPC Builder system using the JTAG circuitry built into Altera FPGAs. Data sheet (PDF)
Common Flash Interface Provides mass storage support. Data sheet (PDF)
UART Provides common serial interface with variable baud rate, parity, stop and data bits, and optional flow control signals. Data sheet (PDF)
Interval Timer Provides a 32 bit timer; can also be used as a periodic pulse generator or system watchdog timer. Data sheet (PDF)
Parallel I/O (PIO) Provides 1- to 32 bit parallel I/O (input, output, and edge-capture) ports. Data sheet (PDF)
Serial Peripheral Interface (SPI) Implements an industry-standard serial peripheral interface with either master or slave protocol. Data sheet (PDF)
DMA Controller Performs bulk data transfers by offloading memory tasks from the CPU. Data sheet (PDF)
SDRAM Controller Provides a simple Avalon® interface to off-chip SDRAM and supports 8, 16, 32 and 64 bit data. Data sheet (PDF)
Memory Interfaces

Includes:

  • On-chip ROM and RAM
  • SDRAM, SSRAM, SRAM, and flash
  • Altera serial configuration devices
Data sheet (PDF)

You can use the SOPC Builder tool to configure your Nios II processor systems. SOPC Builder offers an intuitive wizard-style user interface to configure components, memory-mapped addresses, master/slave relationships, and interrupt priorities. SOPC Builder also makes it easy for you to integrate your own custom-built design blocks as easily as a standard peripheral.

Custom Peripherals

You can create your own custom peripherals and integrate them into Nios II processor systems using the interface-to-user-logic wizard. This automated tool examines Verilog HDL or VHDL source code, identifies top-level ports, and wires these ports up to the appropriate processor bus signals with minimal user assistance. This powerful time-saving device works equally well for custom peripherals and custom instructions. It's easy to iterate a design to determine the best way to optimize a system. Find out more about SOPC Builder.