Nios II Processor Family Questions and Answers

These are the questions that are most frequently asked about Altera’s Nios® II family of embedded processors.

General

Device Support and Licensing

System Design and Construction

Nios II Processor Architecture

Software Tools and Middleware

General

What is the Nios II family of embedded processors?

The Nios II embedded processor family is Altera’s second-generation soft embedded processor solution. The Nios II processor cores are 32 bit RISC processors that share a common instruction set architecture and are optimized for use in all of Altera's mainstream FPGA families. Visit the Nios II processor page for details.

What are the specific benefits of the Nios II family of processors?

The Nios II embedded processors offer the ultimate in embedded design versatility. You can create the perfect fit solution in terms of processors, peripherals, interfaces, and memory.

The key benefit of the Nios II processor is that it is a soft core processor. This means that designers can instantiate as many Nios II processor cores as the programmable fabric will support. This could be as high as over a 100 Nios II processors in a single system. With this amount of flexibility, each Nios II processor may be dedicated to perform a single mission critical task. For instance, a Nios II processor can be dedicated for a real time control function whereas another can be used to run Linux OS to implement a network stack or user interface.

The Nios II/e CPU core was specifically designed to be optimized for the lowest possible logic utilization and, combined with low-cost FPGA families such as the Cyclone® FPGA series, offer processor systems for well under $1.00. Learn more about the low-cost benefits of the Nios II processors.

The Nios II /s and /f core are ideal for real-time applications, especially when absolute real-time determinism is required. The Nios II processors feature Vector Interrupt Controllers that provide low latency interrupt support, tightly coupled memory, custom instruction interfaces that allow the processor to use hardware to execute instructions and support a range of RTOSes.

Developers with high-performance requirements will develop with the Nios II/s or Nios II/f processor cores. The Nios II/f core achieves performance of 200 MHz, and can be accelerated much further by offloading compute-intensive software tasks to Nios II custom instructions and hardware accelerators. Learn more about the high-performance benefits of the Nios II processors.

Finally, the Nios II processors can help you lengthen the life cycle of your products. Using the soft Nios II processors allows you to conveniently deploy in-field upgrades to software or hardware. Finally, because you own the source files to your custom-built Nios II processor system, your product is immune to component obsolescence. You own the processor, and you protect your investment in the system software.

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How many processor cores make up the Nios II processor family?

The Nios II processor is made available as three distinct cores to provide you with maximum design flexibility while balancing system performance needs and logic element (LE) usage. All three cores are included in the Nios II development kits and are supported by the SOPC Builder design tool.

The Nios II processor family is made up of these cores:

  • Nios II/f (fast)–Highest performance, moderate FPGA utilization
  • Nios II/s (standard)–High performance, low FPGA utilization
  • Nios II/e (economy)–Modest performance, lowest FPGA utilization

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What are the benefits of using a soft processor in an FPGA implementation over a hard macro?

By implementing a processor as a hardware description language (HDL)-coded intellectual property (IP) core, you get an exact-fit solution because you can choose the peripheral, performance, and processor mix that best suits your system needs. Hard macro implementations are essentially ASICs and do not have the same flexibility; they take so long to deploy that you can't benefit from the latest process technology. Soft core processors, on the other hand, can migrate immediately to the latest FPGA technology such as the Stratix® or Cyclone FPGA series. Also, standard microprocessor-based solutions are subject to obsolescence issues, whereas Nios II-based solutions resist obsolescence because they are constructed from re-targetable HDL.

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How does the Nios II architecture differ from the first-generation Nios processor?

The Nios II processor has a 32 bit RISC instruction-set architecture, whereas the first-generation Nios processor has a 16 bit instruction-set architecture. The Nios II processor reaches new levels of efficiency and performance over the Nios processor core because it consumes much fewer FPGA resources yet quadruples computational performance. The Nios II processor also simplifies the processor selection process by providing a set of pre-optimized cores targeting specific price (logic usage) and performance constraints.

What market segments does the Nios II processors target?

The Nios II processor family can be used in a wide range of applications that require a general-purpose, 32 bit embedded microprocessor.

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Device Support and Licensing

Which Altera FPGA families support the Nios II processors?

The Nios II processors are fully supported by all Altera SoC, FPGAs, and HardCopy ASICs.

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What is the Nios II processor licensing model?

The Nios II processor IP license is royalty-free, and perpetual which means it allows user to use the Nios II processor IP core forever and has no limit on the number of Nios II processors that can be used in a given design or a project. The Nios II processor IP license entitled a user to one year worth of support from Altera mySupport and feature updates. For new features, and Altera mySupport assistance users must renew their Nios II prcoessor IP licenses if it is not current within two releases of the ACDS version.

Does Altera offer an ASIC migration path for Nios II processor-based systems?

No. Synopsys® provides the Nios II DesignWare IP core, an ASIC optimized version of the Nios II Processor that can be used for ASIC migration as part of their DesignWare IP Suite. Contact Synopsys directly for more details.

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System Design and Construction

What tools are needed to design with the Nios II embedded processor family?

The Nios II Embedded Design Suite (EDS) represents complete development tool suite for both the creation of Nios II processor-based microcontrollers as well as the programming of the target Nios II processor systems.

Can multiple Nios II processor cores be implemented in a single FPGA?

Multi-processor systems are one of the main benefits of the Nios II embedded processors. The only limitation on the number of processor cores is the resource limitation of the FPGA fabric.

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What is the Avalon?

The Avalon® interface specification is used for master and slave components to communicate with each other. For low latency, point-to-point interface, Avalon specifies a simple Avalon Streaming interface (Avalon-ST). For an interface where a processor's master interfaces with a peripheral slave, Avalon specifies an Avalon Memory Mapped interface (Avalon-MM).

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What is system interconnect?

System interconnect is logic that is used to connect master and slave components. This logic might be a bridge, a multiplexor, an arbitration controller. Qsys automatically generates system interconnect logic and connects master and slave ports efficiently allowsing multiple master ports to operate simultaneously, which dramatically boosts system performance.

The Avalon system interconnect is a custom-built interconnect that is automatically generated by Qsys.

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Nios II Processor Architecture

What architectural elements are found in Nios II processor cores?

The Nios II processor family provide the basic architectural elements found in most modern 32 bit processors, including:

  • 32 bit instruction size
  • 32 bit data and address paths
  • 32 general-purpose registers
  • 32 external interrupt sources
  • Configurable instruction cache
  • Configurable data cache
  • Common interface to up to 256 custom instructions
  • Common interface for the integration of custom peripherals

What are custom instructions?

Custom instructions are user-added hardware blocks that augment the arithmetic logic unit (ALU) of a CPU. Nios II processors fully support the use of custom instructions, allowing you to fine-tune your system hardware to meet performance goals. You can create up to 256 custom instructions per Nios II processor core used in the system. Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.

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Software Tools and Middleware

How do developers build software for a Nios II processor system?

The Nios II prcoesspr software development tool automatically generates a customized C/C++ run-time environment tailored to the system hardware. The Nios II Embedded Design Suite also simplifies project setup by supplying several software templates which can be used as “starter” files in developing custom firmware solutions.

What software debug tools are available for use with Nios II processors?

Altera provides a complete software debugging solution via the Nios II EDS that enables debug to occur via an instruction set simulator (ISS) or directly to system hardware. Direct debugging of a Nios II processor system in hardware is enabled through a hardware-assisted debug module. The debug module is rich in features and provides run control, memory examination and modification, hardware breakpoints, data triggers, and processor trace under IDE control.

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What third-party software tools are available for the Nios II processors?

Several top embedded software tools providers offer support for the Nios II family of processors, providing operating systems, middleware, software libraries, IDEs, debuggers, co-verification tools, and more. View the complete list of up-to-date embedded tools providers.


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