Altera’s automotive digital radar reference design lets you easily develop and verify hardware accelerators using our advanced development tools. It demonstrates how an FPGA can be used as a hardware accelerator for basic continuous wave frequency modulation (CWFM) type automotive radars. Its hardware and software design methodology enables you to develop digital radar processing floating-point fast Fourier transform (FFT) accelerators, digital beamforming, and fixed-point finite impulse response (FIR) filtering without hand coding register transfer level (RTL). Use this design as a starting point for radar designs to which you can add additional processing algorithms.
The main features of this reference design are:
- Develop a floating-point FFT hardware accelerator, digital beamformer, and fixed-point FIR filter using our DSP Builder Advanced blockset within MATLAB Simulink. Allows for automatic generation of register transfer level (RTL) from the DSP Builder model.
- Hardware verification of the DSP Builder model using system in the loop via a MATLAB application program interface (API) developed by Altera. Provides ability to verify the design at system clock speed on actual hardware instead of needing to simulate RTL.
- Integrates the hardware accelerator into an embedded system using Qsys system design tool and Nios® processor II as the host.
Demonstrated Altera Technology:
- Cyclone® V GX FPGA
- Nios II processor
- DSP Builder Advanced blockset
- Qsys system design tool
- Quartus® II software tool
- System Console
- MATLAB API