- 3G-serial digital interface (3G-SDI) 1080p60 input
- 3G-SDI 1080p60 output containing up to five output resolutions mixed over a test pattern base layer
- The mixer can be easily bypassed to output each video pipeline separately instead of being blended into one output stream
- Three scaler algorithmic IP cores:
- One with four horizontal and vertical taps for upscale only
- One with 12 horizontal and vertical taps for upscale and up to 3X downscale
- One with 16 horizontal and vertical taps for upscale and up to 4X downscale
- Run-time configuration and initialization in software
- Highly parameterizable, SOPC-ready, modular hardware functions including the Video and Image Processing (VIP) Suite, Nios® processors, and memory controllers
- Runs on the Altera® Stratix® IV GX FPGA Development Kit with one Terasic Transceiver SDI High-Speed Mezzanine Card (HSMC) board.
How Does This Reference Design Work?
The reference design, shown in Figure 2, has four major functional blocks. The video input takes a single SDI input, checks that it is in a supported format, and then sends it to the line buffer components. The next video pipeline component takes the input video, produces the five output resolutions, and writes them to memory. The video output component reads the five output resolutions from external memory, mixes the outputs over a test pattern base layer, and sends the resulting video to the SDI output. The video pipeline components require much lower-level control as they only perform tasks, such as processing input packets, when they receive a command from the scheduler. The DDR3 SDRAM Controller with ALTMEMPHY and the multiport front end buffer the video to and from external DDR3 SDRAM. For more details, refer to the application note 4K Format Conversion Reference Design.
Figure 2. Multioutput Scaler Reference Design Block Diagram
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