FPGA Design Security Solution Using a Secure Memory Device Reference Design

from Altera

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Overview

FPGA designs are vulnerable to design theft because configuration bitstreams can be easily captured and copied. FPGAs are more vulnerable to cloning of the entire design rather than to intellectual property (IP) theft, since extracting IP from the bitstream is nearly impossible. To protect the configuration bitstream, some FPGAs are now capable of encrypting the bitstream. However, there is a high cost for encrypting the configuration bitstream due to the additional step of programming the encryption key in the FPGA during manufacturing. For high-volume applications, using a security companion chip is much more cost effective.

This reference design provides a solution to help protect FPGA designs from being cloned. Using the “identification, friend or foe” (IFF) design security approach, this solution disables the design within the FPGA until the hash algorithm computation matches in both the FPGA and a secure memory device, so the design remains secure even if the configuration data bitstream is captured.

Features

  • Hash Algorithm (SHA-1) encryption core

Demonstrated Altera Technology

Block Diagram

Figure 1. Block Diagram

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These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.