FPGA Design Security Using MAX II Reference Design

from Altera

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Overview

SRAM-based FPGAs are volatile devices. They require external memory to store the configuration data that is sent to them at power up. It is possible for the configuration bitstream to be captured during the transmission and used to configure other FPGAs. This form of intellectual property theft can cause revenue loss to the designer.

This reference design provides a solution to prevent FPGA designs from being copied. It allows the FPGA design to remain secure even if the configuration bitstream is captured. This is accomplished by disabling the functionality of the user design within the FPGA until handshaking tokens are passed to the FPGA from the MAX®II device. The MAX II devices are selected for generating the handshaking tokens because they are non-volatile and retain their configuration data during power down.

Features

  • Triple data encryption standard (3DES) encryption core
  • 32-bit random number generator (RNG)

Demonstrated Altera Technology

BlockDiagram

Figure 1. Block Diagram

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Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.