I2C Controller Reference Design

from Microtronix Inc.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Request this reference design along with an evaluation version of the I2C IP Core.

Overview

The Microtronix inter-IC (I2C) Controller reference design uses the I2C controller intellectual property (IP) along with the Nios® II embedded processor and peripherals. This reference design is built to work on the Nios II development kits specified below.

The I2C bus is a simple two-wire, bidirectional interface developed for I2C communication with Santa Cruz headers and any I2C slave device with compatible pins. This flexible design makes it easy to communicate effectively with the Microtronix I2C board.

The Microtronix I2C IP core is a complete I2C solution offering three modes of operation: I2C master controller, I2C slave controller, and an 8-bit parallel I/O (PIO) slave device. Three I2C bus transmission speeds are supported: 100 Kbps (normal), 400 Kbps (fast), and 3.4 Mbps (high speed). The Microtronix I2C master/slave core provides a generic memory-mapped bus interface. It is also designed as an Altera® SOPC Builder ready component and integrates easily into any SOPC Builder generated system using a Nios II Avalon® system interconnect fabric.

The Microtronix I2C PIO slave core is provided as an Altera Quartus® II megafunction and integrated into the Altera MegaWizard® Plug-In Manager.

Features

  • I2C master/slave transmitter and receiver IP core
  • Nios II embedded processor
  • I2C 8-bit PIO slave core
  • Own address and general call address detection
  • Input clock filter
  • Meets Philips I2C bus specification version 2.1
  • Seven bits addressing format
  • Single byte transmit and receive buffer
  • 300 logic elements (LEs) for Avalon master/slave, 100 LEs for PIO

Demonstrated Altera Technology

Block Diagram

Figure 1 shows an I2C controller system-level diagram.

Figure 1. Microtronix I2C Controller Reference Design Block Diagram


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