Altera offers a PCI Express® (PCIe®) to External Memory reference design that demonstrates the operation of Altera's PCIe-based MegaCore® function with either a DDR2 or DDR3 SDRAM memory controller. This design provides a sample interface between the Altera® PCIe-based MegaCore function and an external 64-bit SDRAM memory.
The PCIe to External Memory reference design is available in clear text Verilog HDL. The design is available for the Qsys design flow which automates the process of connecting the individual components. It is also available in the MegaWizardTM design flow which provides more flexibility in controlling the interconnect fabric.
- Supports PCIe-based endpoint to direct memory access (DMA) read and write transactions
Uses the PCIe-based hard intellectual property (IP) MegaCore function with one of the following memory controllers:
- High-Performance Controller II SDRAM MegaCore function for DDR3
- DDR2 SDRAM High-Performance Controller MegaCore function
- Supports Stratix® IV GX or Arria® II GX FPGAs with internal transceivers
- Supports the Qsys system integration tool
Demonstrated Altera Technology
- Stratix IV GX FPGAs with transceiver technology
- Arria II GX FPGAs with transceiver technology
- Altera PCIe-based MegaCore function
- Altera High-Performance Controller II SDRAM MegaCore function
- Altera DDR2 SDRAM High-Performance Controller MegaCore function
- Altera Qsys system integration tool