The Serial RapidIO® (SRIO) interoperability reference design provides an example interface connection between the Altera® RapidIO MegaCore® function and the Texas Instruments TMS320TCI6488 Communications Infrastructure Digital Signal Processor (TI 6488 DSP or TI 6488). The reference design enables the evaluation of the SRIO MegaCore function for integration into an Altera FPGA.
In addition to demonstrating basic interoperability, the reference design includes link utilization measurement in all modes, at all SRIO data rates, and for all supported packet sizes.
- Programs the SRIO MegaCore function to initiate write transaction types targeted to the TI 6488 DSP
- Programs the SRIO MegaCore function to any Serial RapidIO MegaCore 1x lane, data rate (up to 3.125 gigabaud), and supported packet size variant
- Includes support for gathering statistics
- Connects a Stratix® IV GX FPGA development board or an Arria® II GX FPGA development board to a Spectrum Digital, Inc. TI 6488 DSP Evaluation Module (EVM), which includes the Texas Instruments Code Composer Studio (CCS) software to program and monitor the TI 6488 processor through a high-speed mezzanine card (HSMC) to an advanced mezzanine card (AMC)
- Step-by-step walk-through instructions and complete design files (including Quartus® II software archive)
Demonstrated Altera Technology
- Stratix IV GX FPGAs
- Arria II GX FPGAs
- Altera Serial RapidIO MegaCore intellectual property (IP)