Crest Factor Reduction Reference Design for Wireless Systems

Please contact your local sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.

The Crest Factor Reduction reference design is a high-performance, highly parameterizable crest factor reduction processor, designed and delivered using the DSP Builder for Intel® FPGAs (Advanced Blockset) tool. It is based on the peak cancellation algorithm.

The design methodology allows you to go from system definition and simulation, using the industry-standard MathWorks* Simulink* tools, to system implementation in a matter of minutes. System definition in both fixed and floating-point number representations is supported. The DSP Builder for Intel FPGAs (Advanced Blockset) uses a high-level synthesis technology that optimizes the untimed netlist into low-level, pipelined hardware targeted to your chosen FPGA device and chosen clock rate. It provides a constraint-driven design methodology through system-level parameters. You specify the desired f; the tool then inserts sufficient pipelining, balances delays and maintains the datapath algorithm accuracy. The result is that the DSP Builder for Intel FPGAs (Advanced Blockset) produces an implementation that is optimized to the same level as hand-coded HDL so the designer does not have to make a design productivity verses efficient implementation compromise.

For system engineers, the DSP Builder for Intel FPGAs (Advanced Blockset) introduces them to FPGA design without having to immediately comprehend all of the tradeoffs associated with other hardware design flows. For hardware engineers, it allows designs to be completed in an abstract format, eliminating the need for timing closure through auto-pipelining and generation of any control logic. To further optimize the design flow, the DSP Builder for Intel FPGAs (Advanced Blockset) allows a common development environment and testbench to be used in developing complex algorithms. This facilitates rapid implementation of changes at the system level, and eliminates barriers between system algorithm and FPGA hardware engineering efforts.

For the Crest Factor Reduction reference design, the DSP Builder for Intel FPGAs (Advanced Blockset) offers a high-level design entry point that lets designers explore the design space and easily customize their design parameters. It also provides a path to easy integration into the Platform Designer (formerly Qsys).

For further information, contact your local representative.

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