3GPP UMTS Turbo Decoder Reference Design

from Altera

Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Overview

FPGAs are well suited for processing intensive tasks such as turbo decoding which requires high throughput and low latency. Support for varying configurations such as multiple sectors, support for WCDMA/HSPA/HSPA+ as well as target BTS form factors such as macro, micro, pico, and femto basestations (BTS) requires a scalable solution. Altera’s UMTS Turbo Decoder reference design is based on the 3GPP specification (TS 25.212 v3.3.0, June 2000) and provides a scalable solution. The solution is based on extensive systems analysis that provides the required throughput with a resource-efficient architecture and superior performance, including bit-error rate (BER) and latency. This reference design was tested and validated against an extensive verification methodology. The solution also offers a choice of run-time and compile-time parameters.

Other deliverables that might also be of interest include:

  • C/MATLAB bit-accurate models for performance simulation or register transfer level (RTL) test vector generation
  • Generation of VHDL or Verilog HDL test benches using the MegaWizard® Plug-In Manager

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