Stratix 10 MX: 1 TBps Memory Bandwidth in a Single FPGA

By 2020 there will be 1 ZB of data center traffic1, 50 B interconnected devices2, 8K video broadcasts3, and 400G4 networking systems.  You need a solution that can handle what’s coming. Intel® Stratix® 10 MX devices, featuring DRAM system-in-package (SiP), provide:

White Paper: Stratix 10 MX Devices Solve the Memory Bandwidth Challenge

Read about the limitations of conventional memory solutions and how DRAM SiP devices deliver better performance at lower power. 

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Stratix 10 MX devices combine the programmability and flexibility of Stratix 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The HyperFlex FPGA core fabric architecture enables a 1 GHz core fabric that can efficiently utilize the bandwidth from the in-package memory tile. The DRAM memory tile is physically connected to the FPGA using Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology.

Stratix 10 MX devices offer extensive system-level integration that includes:

Stratix 10 MX devices address memory bandwidth challenges and enable the the most demanding applications in the high performance computing (HPC), data centers, broadcast, wireline networking, and military markets.

Expanded Memory Hierarchy

Higher Memory Bandwidth

Stratix 10 MX devices offer 10X more bandwidth versus current discrete memory solutions such as DDR4. Traditional DDR4 DMMs provide ~21 GBps bandwidth while 1 HBM2 tile provides 256 GBps.

Stratix 10 MX devices integrate up to four HBM2 devices in a single package, enabling a maximum memory bandwidth of up to 1 TBps.

Lower Power Solution

Stratix 10 MX devices integrate HBM2 memory next to the core fabric. The interconnect between the core fabric and memory is significantly shorter, thereby reducing the amount of power traditionally spent driving long PCB traces. The traces are unterminated and there is reduced capacitive loading, which results in lower I/O current consumption. The net result is lower system power and optimum performance per watt.

 

Smaller Form Factor and Ease of Use

Because the Stratix 10 MX package contains integrated memory components, the PCB design has reduced routing complexity. This implementation enables a smaller form factor and a simple usage model. The net result is a highly flexible, scalable solution that is easy to use.

Enhanced Embedded SRAM

Stratix 10 MX devices offer fast path, low-latency on-chip memory through embedded SRAM (eSRAM). eSRAM supplements already existing block RAM. eSRAM features include:

  • Higher Bandwidth: 11.25X more aggregate (read and write) bandwidth relative to discrete QDR IV-1066
  • Lower Power: 2.6X total lower power compared to discrete QDR IV (Watts/Gbps)
  • Ease of Use: Direct fabric interface, no controller needed, reduced consumption of M20K blocks
  • Reduced Board Cost and Complexity:
    • Reduced PCB congestion and layer count
    • Helps replace or minimize the need for discrete QDR
    • Zero EMIF I/O consumption
  • Ideal for applications requiring highest levels of random transaction rates (RTR)

Footnotes:

  1. Evans, Dave, Cisco Internet Business Solutions Group (CIBSG).  The Internet of Things – How the Next Evolution of the Internet is Changing Everything, April 2011.
  2. Cisco, Cisco Global Cloud Index: Forecast and Methodology, 2014–2019, 2015.
  3. CNET, 8KTV broadcasting coming to Japan during 2016 Olympics, March 7, 2016.
  4. www.ethernetalliance.org. Ethernet Roadmap. 2015.
Stratix 10 MX Family Overview Table
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