Overview

Altera SoCs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone.

Altera SoCs: When Architecture Matters

Altera SoCs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic.

These user-customizable ARM-based SoCs are ideal for:

  • Reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA
  • Improving system performance via high-bandwidth interconnect between the processor and the FPGA
  • Differentiating your end product by customizing in both hardware and software
  • Developing ARM-compatible software with unmatched target visibility, control, and productivity using Altera's exclusive FPGA-adaptive debugging

These devices include additional hard logic such as PCI Express® Gen2, multiport memory controllers, error correction code (ECC), memory protection and high-speed serial transceivers. The ARM-compatible software provides unmatched target visibility, control, and productivity using Altera's exclusive FPGA-adaptive debugging.

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Not All SoC FPGAs Are Created Equal. Architecture Matters.

Learn how to choose the right SoC FPGA for your application from our extensive set of resources, including a short series of videos from processor expert Jim Turley.

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Architecture Matters

Building a product with a strong architecture is key to ensuring that your system design meets its performance requirements now and into the future. With Altera SoCs for embedded systems, you begin with a solid foundation that brings your design:

  • Improved system performance through a higher hard processor system (HPS) to FPGA bandwidth interconnect, hardware acceleration, and increased memory performance
  • Increased reliability through error correction code (ECC) and memory protection that help protect systems against potential hardware or software errors and warm/cold CPU reset that initiates without affecting or reprogramming the FPGA
  • More flexibility through hardware differentiation, system boot and configuration options, and multiple hardened memory controllers
  • Lower system cost through single-chip integration, integrated PCIe® controller, and no power off sequencing
  • Increased productivity through our FPGA-adaptive debugging tool with unmatched target visibility, control, and productivity
  • Path for the future through our roadmap for high-end, mid-range, and low-end applications, forward migration of software, and products with average life cycles of 15 years or more

Learn More >> Choosing the Right SoC FPGA for Your Application