Intel® FPGAs offer a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Built in intellectual property (IP) combined with outstanding software tools lower FPGA development time, power and cost.
Intel SoCs: When Architecture Matters
Intel SoCs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic.
These user-customizable ARM-based SoCs are ideal for:
- Reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA
- Improving system performance via high-bandwidth interconnect between the processor and the FPGA
- Differentiating your end product by customizing in both hardware and software
- Developing ARM-compatible software with unmatched target visibility, control, and productivity using our FPGA-adaptive debugging
These devices include additional hard logic such as PCI Express® Gen2, multiport memory controllers, error correction code (ECC), memory protection and high-speed serial transceivers. The ARM-compatible software provides unmatched target visibility, control, and productivity using our FPGA-adaptive debugging.
Learn how to choose the right SoC FPGA for your application from our extensive set of resources, including a short series of videos from processor expert Jim Turley.
Building a product with a strong architecture is key to ensuring that your system design meets its performance requirements now and into the future. With our SoCs for embedded systems, you begin with a solid foundation that brings your design:
- Improved system performance through a higher hard processor system (HPS) to FPGA bandwidth interconnect, hardware acceleration, and increased memory performance
- Increased reliability through error correction code (ECC) and memory protection that help protect systems against potential hardware or software errors and warm/cold CPU reset that initiates without affecting or reprogramming the FPGA
- More flexibility through hardware differentiation, system boot and configuration options, and multiple hardened memory controllers
- Lower system cost through single-chip integration, integrated PCIe® controller, and no power off sequencing
- Increased productivity through our FPGA-adaptive debugging tool with unmatched target visibility, control, and productivity
- Path for the future through our roadmap for high-end, mid-range, and low-end applications, forward migration of software, and products with average life cycles of 15 years or more