Intel® Arria® 10 SoCs, based on TSMC’s 20 nm process technology, combine a feature-rich dual-core ARM* Cortex*-A9 MPCore* hard processor system (HPS) with industry-leading programmable logic technology. The Arria 10 SoCs offer a processor with rich feature set of embedded peripherals, hardened floating-point variable-precision digital signal processing (DSP) blocks, high-speed transceivers, hard memory controllers,  Secure boot capability, using Elliptic Curve Digital Signature Algorithm (ECDSA) and Advanced Encryption Standard (AES), and protocol intellectual property (IP) controllers all in a single highly integrated package.

Arria 10 SoC Block Diagram

Arria 10 SoC Feature Overview

See the tables below for an overview of the Arria 10 SoC FPGA family and package choices. The HPS is common to all the devices in the famlly.

Table 1: Arria 10 SoC Hard Processor System Features

Feature Description
Processor Dual-core ARM Cortex-A9 MPCore processor with ARM CoreSight* debug and trace technology
Coprocessors Vector floating-point unit (VFPU) single and double precision, ARM NEON* media processing engine for each processor snoop control unit (SCU), acceleration coherency port (ACP)
Level 1 cache 32 KB L1 instruction cache, 32 KB L1 data cache
Level 2 cache 512 KB shared L2 cache
Scratch pad RAM 256 KB
HPS DDR memory DDR4 and DDR3 (up to 64 bit with error correction code (ECC))
Direct memory access (DMA) controller 8-channel direct memory access (DMA)
Ethernet media access controller (EMAC) 3 x 10/100/1000 EMAC with integrated DMA
USB On-The-Go controller (OTG) 2x USB OTG with integrated DMA
UART controller 2x UART 16550 compatible
Serial peripheral interface (SPI) controller 4x SPI
I2C controller 5x I2C
QSPI flash controller 1x SIO, DIO, QIO SPI flash supported
SD/SDIO/MMC controller 1x eMMC 4.5 with DMA and CE-ATA support
NAND flash controller 1x ONFI 1.0 or later 8 and 16 bit support
General-purpose I/O (GPIO) Maximum 62 software-programmable GPIO
Timers 7X general-purpose timers, 4X watchdog timers
Security Secure boot, Advanced Encryption Standard (AES) and authentication based on Elliptic Curve Digital Signature Algorithm (ECDSA)

Table 2: Arria 10 SoC Family Plan

Part Number Reference 10AS016 10AS022 10AS027 10AS032 10AS048 10AS057 10AS660
Arria 10 SoC Product Line SX 160 SX 220 SX 270 SX 320 SX 480 SX 570 SX 660

Logic elements (LEs) (K)

160

220

270

320

480

570

660

Adaptive logic modules (ALMs)

61,510

83,730

101,620

118,730

181,720

217,080

250,450

Registers

246,040

334,920

406,480

474,920

727,160

868,320

1,002,160

M20K memory blocks

440

588

750

891

1,438

1,800

2,133

M20K memory (Mb)

9

11

15

17

28

35

42

MLAB counts

1,680

2,227

3,968

4,673

7,137

8,241

9,345

MLAB memory (Mb)

1.0

1.8

2.4

2.8

4.3

5.0

5.7

Variable-precision DSP blocks

156

191

830

985

1,368

1,523

1,688

18 X 19 multipliers

312

382

1,660

1,970

2,736

3,046

3,376

Peak GMACS

343

420

1,826

2,167

3,010

3,351

3,714

Single-precision floating-point multipliers

156

191

830

985

1,368

1,523

1,688

Single-precision floating-point adders

156

191

830

985

1,368

1,523

1,688

Peak giga floating-point operation per second (GFLOPs)

140

172

747

887

1,231

1,371

1,519

Maximum GPIOs

288

288

384

384

492

696

696

Maximum transceiver count (17.4 G)

12

12

24

24

36

48

48

Fractional PLLs

6

6

8

8

12

16

16

I/O PLLs

6

6

8

8

12

16

16

PCIe* Gen3 x8 hard IP blocks

1

1

2

2

2

2

2

Hard memory controller (1)

Supports DDR4 / DDR3 / DDR2/ LPDDR3 / LPDDR2 / RLDRAM 3/ RLDRAMII / QDR IV / QDR II+ / QDR II SRAM. Supports DDR4/DDR3/LPDDR3 for processor memory.

Table 3: Arria 10 SoC Small Form Factor Packages

Device U19 (U484)
(19x19 mm2)
F27 (F672)
(27x27 mm2)
F29 (F780)
(29x29 mm2)
  GPIO 3 V I/O LVDS XCVR GPIO 3 V I/O LVDS XCVR GPIO 3 V I/O LVDS XCVR

10AS016

192 48 72 6 240 48 96 12 288 48 120 12

10AS022

192 48 72 6 240 48 96 12 288 48 120 12

10AS027

- - - - 240 48 96 12 360 48 156 12

10AS032

- - - - 240 48 96 12 360 48 156 12

10AS048

-

-

-

-

-

-

-

-

360

48

156

12

Table 4: Arria 10 SoC I/O and Transceiver (XCVR)-Optimized Packages

Device F34
(35x35 mm2)
(H = 24 XCVRs)
F35
(35x35 mm2)
(K = 36 XCVRs)
F40
(40x40 mm2)
(N = 48 XCVRs)

F40
(40x40 mm2)
(K = 36 XCVRs)

GPIO 3 V I/O LVDS XCVR GPIO 3 V I/O LVDS XCVR GPIO 3 V I/O LVDS XCVR GPIO 3 V I/O LVDS XCVR
10AS027

384

48

168

24

384

48

168

24

-

-

-

-

-

-

-

-

10AS032

384

48

168

24

384

48

168

24

-

-

-

-

-

-

-

-

10AS048

492

48

222

24

396

48

174

36

-

-

-

-

-

-

-

-

10AS057

492

48

222

24

396

48

174

36

588

48

270

48

648

96

324

36

10AS066

492

48

222

24

396

48

174

36

588

48

270

48

648

96

324

36

Notes:

  1. All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch.
  2. High-voltage I/O pins are used for 3.3 V and 2.5 V interfacing.
  3. Each LVDS pair can be configured as either a differential input or a differential output.
  4. High-voltage I/O pins and LVDS pairs are included in the general-purpose I/O count. Transceivers are counted separately.
  5. The F40 package with 36 XCVRs (K package) offers 72 bit DDR support for HPS memory. All other packages offer 40 bit HPS DDR memory.