The Arria® V SoC integrates a dual-core ARM* Cortex*-A9 Hard Processor System (HPS), embedded peripherals, multiport memory controllers, serial transceivers, PCI Express* (PCIe*) ports and Arria V FPGA fabric into a single, high-performance device.

Arria V SoC Architecture

Table 1. Arria V SoC Hard Processor System Overview

Device All Arria V SoC Devices (SX, ST)
Processor

Dual-core ARM Cortex-A9 MPCore processor with ARM CoreSight* debug and trace technology

  • 1.05 GHz CPU clock rate in -I3 speed grade
  • 925 MHz CPU clock rate in -C4 speed grade
  • 800 MHz CPU clock rate in -C5, -I5 speed grades
  • 700 MHz CPU clock rate in -C6 speed grade
Coprocessors ARM NEON* media processing engine with Vector Floating-Point (VFP) v3 double-precision floating point unit for each processor, Snoop Control Unit (SCU), Acceleration Coherency Port (ACP)
Level 1 cache 32 KB L1 instruction cache, 32 KB L1 data cache
Level 2 cache 512 KB shared L2 cache
On-chip memory 64 KB on-chip RAM, 64 KB on-chip ROM
HPS hard memory controller

Multiport SDRAM controller with support for DDR2, DDR3, DDR3L, and LPDDR2 with optional error correction code (ECC) support
533 MHz/1066 Mbps external memory interface
User-configurable memory width of 8, 16, 16+ECC, 32, 32+EEC
Up to 4 GB address range, with built-in memory protection control

Quad serial peripheral interface (SPI) flash controller Supports SPIx1, SPIx2, or SPIx4 (quad SPI) serial NOR flash devices
Up to four chip selects
SD/SDIO/MMC controller

Supports SD, eSD, SDIO, eSDIO, MMC, eMMC, and CE-ATA with integrated DMA

NAND flash controller Supports 8 bit ONFI 1.0 NAND flash devices
Programmable hardware ECC for Single-Level Cell (SLC) and Multi-Level Cell (MLC) devices
Ethernet media access controller (EMAC) 2 x 10/100/1000 EMAC with RGMII external PHY interface and integrated DMA
USB On-The-Go controller (OTG) 2 x USB 2.0 OTG controllers with ULPI external PHY interface and integrated DMA
UART controller 2 x UART 16550 compatible
SPI controller 2 x SPI masters
2 x SPI slaves
I2C controller 4 x I2C
General-purpose I/O (GPIO) Up to 71 GPIO and 14 input-only pins, with digital de-bounce and configurable interrupt mode
Direct memory access (DMA) controller 8-channel direct memory access (DMA)
Supports flow control with 31 peripheral handshake interfaces
Timers Private interval and watchdog timer for each processor
Global timer for processor subsystem
4X general-purpose timers
2X watchdog timers
Maximum HPS I/O 208
HPS phased-locked loops (PLLs) 3

Table 2. Arria V SoC Device Family Variations

Variant Description
Arria V SX SoC Intel® SoC FPGA with ARM-based HPS and 6.5536 Gbps backplane-capable transceivers
Arria V ST SoC Intel SoC FPGA with ARM-based HPS and 10.3125 Gbps transceivers

Table 3. Arria V SX SoC Overview

Device 5ASXB3 5ASXB5
Processor cores (ARM Cortex-A9 MPCore)
Dual
Dual
Logic elements (LEs) (K)
350,000
462,000
Adaptive logic modules (ALMs)
132,075
174,340
M10K memory blocks
1,729
2,282
M10K memory (Kb)
17,290
22,820
MLABs (Kb)
2,014
2,658
18x19 multipliers
1,618
2,180
Variable-precision digital signal processing (DSP) blocks (1)
809
1,090
Maximum transceivers (6.5536 Gbps)
30
30
PCI Express (PCIe) hard intellectual property (IP) blocks
2
2
Maximum HPS I/O
208
208
Maximum FPGA user I/Os
540
540

Maximum FPGA LVDS

256
256
HPS PLLs
3
3
FPGA fractional PLLs
14
14

HPS hard memory controllers

1
1
FPGA hard memory controllers
3
3

Note:
1. DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.

Table 4. Arria V SX SoC Package Overview and User I/O Pins (FPGA I/O, HPS I/O Pins Transceivers)

Device/Package
(mm x mm)
F896 F1152 F1517
1.0 mm
31 x 31
1.0 mm
35 x 35
1.0 mm
40 x 40
FPGA
I/Os
HPS
I/Os
Maximum
Transceivers
(6.5536 Gbps)
FPGA
I/Os
HPS
I/Os
Maximum
Transceivers
(6.5536 Gbps)
FPGA
I/Os
HPS
I/Os
Maximum
Transceivers
(6.5536 Gbps)
5ASXB3
250
208
12
385
208
18
540
208
30
5ASXB5
250
208
12
385
208
18
540
208
30

Table 5. Arria V ST SoC Overview

Device 5ASTD3 5ASTD5
Processor cores (ARM Cortex-A9 MPCore)
Dual
Dual
LEs (K)
350,000
462,000
ALMs
132,075
174,340
M10K memory blocks
1,729
2,282

M10K memory (Kb)

17,290
22,820
MLABs (Kb)
2,014
2,658
18x19 multipliers
1,618
2,180
Variable-precision DSP blocks (1)
809
1,090
Maximum transceivers (6.5536 Gbps/10.3125 Gbps) (2, 3)
30/16
30/16

PCIe hard IP blocks

2
2
Maximum HPS I/O
208
208
Maximum FPGA user I/Os
540
540
Maximum FPGA LVDS
256
256

HPS PLLs

3
3
FPGA fractional PLLs
14
14
HPS hard memory controllers
1
1
FPGA hard memory controllers
3
3

Note:
1. DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.
2. 10 Gbps transceivers are for chip-to-chip connections only.
3. Each set of three 6.5536 Gbps transceivers can be configured as two 10 Gbps transceivers with the exception of the two sets nearest the PCIe hard IP, which have a maximum rate of 6.5536 Gbps.

Table 6. Arria V ST SoC Package Overview and User I/O Pins (I/O Pins, Transceivers)

Device/Package
(mm x mm)
F896 F1152 F1517
1.0 mm
31 x 31
1.0 mm
35 x 35
1.0 mm
40 x 40
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps/ 10.3125 Gbps)
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps/ 10.3125 Gbps)
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps/
10.3125 Gbps)(1)
5ASTD3
250
208
12 / 6
385
208
18 / 8
540
208
30 / 16
5ASTD5
250
208
12 / 6
385
208
18 / 8
540
208
30 / 16

Note:
1. Each set of three 6.5536 Gbps transceivers can be configured as two 10 Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.5536 Gbps.

Table 7. Temperature Support

Device Package Speed Grade
Arria V SX F896, F1152, F1517 C4, C5, C6, I3, I5
Arria V ST F896, F1152, F1517 I3, I5