Altera’s Arria® V SoC is the industry's highest performance 28 nm SoC FPGA with the lowest total power for midrange applications such as remote radio units, 10G/40G line cards, medical imaging, and broadcast studio equipment. The combination of a hard processor system (HPS) consisting of a dual-core ARM® Cortex™-A9 processor, peripherals, and memory interfaces with flexible 28 nm FPGA fabric lets you reduce system power, cost, and board space.

Industry’s Highest Performance 28nm SoC FPGA

  • Up to 1.05 GHz dual-core ARM® Cortex™-A9 MPCore processor
  • 4 hardened 32-bit memory controllers with up to 533 MHz memory bus speed and optional ECC
  • Processor to FPGA interconnect with >125 Gbps peak total bandwidth

Lowest System Power for Midrange Applications

  • Integration of multiple components into a single chip
  • Lowest power transceivers with speeds up to 10.3125 Gbps
  • Based on low power TSMC 28LP process

Multiple Benefits to System Cost

Applications

The Arria V SoCs have been designed to meet the performance, power, and cost requirements for applications such as:

  • Wireless infrastructure equipment including remote radio units and mobile backhaul
  • Wireline 10G/40G line cards, bridges and aggregation, GPON
  • Broadcast studio and distribution equipment including professional A/V and video conferencing
  • Military guidance, control, and intelligence equipment
  • Test and measurement equipment
  • Medical imaging equipment
  • Multifunction Printers

Architecture Matters

SoCs are more than the sum or their parts. It is critically important to understand how the processor and FPGA systems work together to accomplish each task. When you choose an SoC for your next design architecture matters. Altera SoCs are designed to:

  • Preserve the flexibility of processor boot / FPGA configuration sequence, system response to processor reset, and independent memory interfaces of a two-chip solution
  • Maintain data integrity and reliability with integrated error correction code (ECC)
  • Protect DRAM memory shared by the processor and FPGA with an integrated memory protection unit
  • Enable system-level debug with Altera’s FPGA-adaptive debugging for unmatched visibility and control of the whole device

Not All SoC FPGAs Are Created Equal. Architecture Matters.

Learn how to choose the right SoC FPGA for your application from our extensive set of resources, including a short series of videos from processor expert Jim Turley.

Learn More >>

Comparison of Arria V SoC Variants

Feature Arria V SX SoC Arria V ST SoC
Processor Dual-core ARM CortexTM-A9 MPCoreTM
Processor Performance 1.05 GHz
Logic Density Range 350 – 462K LE
Embedded Memory 23 Mb
18x19 Multipliers 2,180
Max Transceivers (6 Gbps/10 Gbps) 30/0 30/16
Max Transceiver Data Rate (Chip to Chip) 6.5536 Gbps 10.3125 Gbps
Memory Devices Supported (Hard Memory Controllers) x1 32 bit, 533 MHz DDR3 w/ ECC – HPS
x3 32 bit, 533 MHz, DDR3 - FPGA
Hard Protocol IP

x2 10/100/1000 EMAC – HPS
x2 PCIe® Gen2 x8 - FPGA

Easy Migration Path to Arria 10 SoC

The Arria V SoC and Arria 10 SoC utilize the same dual-core ARM Cortex-A9 processor. Therefore, when your Arria V SoC design is ready for a performance upgrade you can easily migrate your software to the Arria 10 SoC. Based on the TSMC 20 nm process, the Arria 10 SoC  offers for a performance upgrade path for Arria V SoC designs with easy software migration.

Architecture Matters
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