Cyclone® V SoCs offers a powerful dual-core ARM* Cortex*-A9 MPCore* processor surrounded by a rich set of peripherals and a hardened memory controller. The FPGA fabric, with up to 110K LEs (logic elements), is connected to the hard processor system (HPS) through a high-speed >100 Gbps interconnect backbone.

Cyclone V SoC Architecture

Table 1. Cyclone V SoC Family Hard Processor System Overview

Device All Cyclone V SoC Devices (SE, SX, ST)
Processor

ARM Cortex-A9 MPCore processor with ARM CoreSight* debug and trace technology (single and dual-core variants)

  • 925 MHz CPU clock rate in -C6 speed grade
  • 800 MHz CPU clock rate in -C7, -I7 speed grades
  • 700 MHz CPU clock rate in -A7 speed grade
  • 600 MHz CPU clock rate in -C8 speed grade
Coprocessors ARM Neon* media processing engine with vector floating-point (VFP) v3 double-precision floating-point unit for each processor, snoop control unit (SCU), acceleration coherency port (ACP)
Level 1 cache 32 KB L1 instruction cache, 32 KB L1 data cache
Level 2 cache 512 KB shared L2 cache
On-chip memory 64 KB on-chip RAM, 64 KB on-chip ROM
HPS hard memory controller Multiport SDRAM controller with support for DDR2, DDR3, DDR3L and LPDDR2 with optional error correction code (ECC) support
400 MHz/800 Mbps external memory interface
User-configurable memory width of 8, 16, 16+ECC, 32, 32+EEC
Up to 4 GB address range with built-in memory protection control
Quad serial peripheral interface (SPI) flash controller Supports SPIx1, SPIx2, or SPIx4 (quad SPI) serial NOR flash devices
Up to 4 chip selects
SD/SDIO/MMC controller Supports SD, eSD, SDIO, eSDIO, MMC, eMMC, and CE-ATA with integrated direct memory access (DMA)
NAND flash controller Supports 8 bit ONFI 1.0 NAND flash devices
Programmable-hardware ECC for single-level cell (SLC) and multilevel cell (MLC) devices
Ethernet media access controller (EMAC) 2X 10/100/1000 EMAC with RGMII external PHY interface and integrated DMA
USB On-The-Go controller (OTG) 2X USB 2.0 OTG controllers with ULPI external PHY interface and integrated DMA
UART controller 2X UART 16550 compatible
SPI controller

2X SPI masters
2X SPI slaves

I2C controller 4X I2C
CAN controller 2X CAN
Protocol specification 2.0 (A and B)
General-purpose I/O (GPIO) Up to 71 GPIO and 14 input-only pins, with digital de-bounce and configurable interrupt mode
Direct memory access (DMA) controller 8-channel DMA
Supports flow control with 31 peripheral handshake interfaces
Timers Private interval and watchdog timer for each processor
Global timer for processor subsystem
4X general-purpose timers
2X watchdog timers
Maximum HPS I/O 181
HPS phased-lock loops (PLLs) 3

Table 2. Cyclone V SoC Variations

Variant Description
Cyclone V SE SoC Optimized for lowest system cost and power for a wide spectrum of general logic and digital signal processing (DSP) applications
Cyclone V SX SoC Optimized for lowest cost and power for 614 Mbps to 3.125 Gbps transceiver and PCIe-enabled applications
Cyclone V ST SoC FPGA industry’s lowest cost and power for 6.144 Gbps transceiver and PCIe-enabled applications (1)
Notes:
  1. Cyclone V ST SoCs support 6.144 Gbps Common Public Radio Interface (CPRI) protocol

Table 3. Cyclone V SE SoC Family Overview

Device 5CSEA2 5CSEA4 5CSEA5 5CSEA6
Processor cores (ARM Cortex-A9 MPCore)
Single and dual
Single and dual
Single and dual
Single and dual
Logic elements (LEs) (K)
25
40
85
110
Adaptive logic modules (ALMs)
9,434
15,094
32,075
41,509
M10K memory blocks
140
270
397
557
M10K memory (Kb)
1,400
2,700
3,970
5,570
MLABs (Kb)
138
231
480
621
18x19 multipliers
72
168
174
224
Variable-precision DSP blocks (1)
36
84
87
112
Maximum HPS I/O
181
181
181
181
Maximum FPGA user I/Os
145
145
288
288
Maximum FPGA LVDS
69
69
144
144
HPS PLLs
3
3
3
3
FPGA fractional PLLs
5
5
6
6
HPS hard memory controllers
1
1
1
1
FPGA hard memory controllers
1
1
1
1

Note:

1. DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.

Table 4. Cyclone V SE SoC Packages and Maximum User I/Os

Device/ Package
(mm x mm)
U484 U672 F896
0.8 mm
19 x 19
0.8 mm
23 x 23
1.0 mm
31 x 31
FPGA I/Os HPS I/Os FPGA I/Os HPS I/Os FPGA I/Os HPS I/Os
5CSEA2
66
151
145
181
-
-
5CSEA4
66
151
145
181
-
-
5CSEA5
66
151
145
181
288
181
5CSEA6
66
151
145
181
288
181

Table 5. Cyclone V SX SoC Family Overview

Device 5CSXC2 5CSXC4 5CSXC5 5CSXC6
Processor cores (ARM Cortex-A9 MPCore)
Dual
Dual
Dual
Dual
LEs (K)
25
40
85
110
ALMs
9,434
15,094
32,075
41,509
M10K memory blocks
140
270
397
557
M10K memory (Kb)
1,400
2,700
3,970
5,570
MLABs (Kb)
138
231
480
621
18x19 multipliers
72
168
174
224
Variable-precision DSP blocks (1)
36
84
87
112
Maximum transceivers
6
6
9
9
PCI Express® (PCIe®) hard IP block
2
2
2 (2)
2 (2)
Maximum HPS I/Os
181
181
181
181
Maximum FPGA user I/Os
145
145
288
288
Maximum FPGA LVDS
69
69
144
144
HPS PLLs
3
3
3
3
FPGA fractional PLLs
5
5
6
6
HPS hard memory controllers
1
1
1
1
FPGA hard memory controllers
1
1
1
1

Note:

1. DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.
2. One PCIe Hard IP block in U672 package.

Table 6. Cyclone V SX SoC Packages and Maximum User I/Os

Device/Package
(mm x mm)
U672 F896
0.8 mm
23 x 23
1.0 mm
31 x 31
FPGA I/Os HPS I/Os Transceivers FPGA I/Os HPS I/Os Transceivers
5CSXC2
145
181
6
-
-
-
5CSXC4
145
181
6
-
-
-
5CSXC5
145
181
6
288
181
9
5CSXC6
145
181
6
288
181
9

Table 7. Cyclone V ST SoC Family Overview

Device 5CSTD5 5CSTD6
Processor cores (ARM Cortex-A9 MPCore)
Dual
Dual
LEs (K)
85
110
ALMs
32,075
41,509
M10K memory blocks
397
557
M10K memory (Kb)
3,970
5,570
MLAB (Kb)
480
621
18x 19 multipliers
174
224
Variable-precision DSP blocks (1)
87
112
Maximum transceivers
9
9
PCIe hard IP block
2
2
Maximum HPS I/Os
181
181
Maximum FPGA user I/Os
288
288
Maximum FPGA LVDS
144
144
HPS PLLs
3
3
FPGA fractional PLLs
6
6
HPS hard memory controllers
1
1
FPGA hard memory controllers
1
1

Note:

1. DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.

Table 8. Cyclone V ST SoC Device Packages and Maximum User I/Os

Device/Package
(mm x mm)
F896
1.0 mm
31 x 31
FPGA I/Os HPS I/Os Transceivers
5CSTD5
288
181
9
5CSTD6
288
181
9

Table 9. Temperature Support

Device Package Speed Grade
Cyclone V SE
U484, U672, F896
C6, C7, C8, I7, A7
Cyclone V SX
U672, F896
C6, C7, C8, I7, A7
Cyclone V ST
F896
I7