Cyclone V SoCs: Lowest System Cost and Power

Altera's Cyclone® V SoCs provide the industry's lowest system cost and power. The SoCs’ high-performance levels are ideal for differentiating high-volume applications, such as industrial motor control drives, protocol bridging, video converter and capture cards, and handheld devices. SoCs come in a wide range of programmable logic densities with many system-level functions hardened in silicon — a dual-core ARM® Cortex®-A9 hard processor system (HPS), embedded peripherals, multiport memory controllers, serial transceivers, and PCI Express® (PCIe®) ports.

ARM-Based HPS

The Cyclone V SoC HPS consists of a dual-core ARM Cortex-A9 MPCore™ processor, a rich set of peripherals, and a multiport memory controller shared with logic in the FPGA, giving you the flexibility of programmable logic and the cost savings of hard intellectual property (IP) due to:

  • Single- or dual-core processor with up to 925 MHz maximum frequency
  • Hardened embedded peripherals eliminate the need to implement these functions in programmable logic, leaving more FPGA resources for application-specific custom logic and reducing power consumption
  • Hardened multiport memory controller, shared by the processor and FPGA logic, supports DDR2, DDR3, and LPDDR2 devices with integrated error correction code (ECC) support for high-reliability and safety-critical applications

High-Bandwidth Interconnect

High-throughput datapaths between the HPS and FPGA fabric provide interconnect performance not possible in two-chip solutions. This tight integration provides:

  • Over 100 Gbps peak bandwidth
  • Integrated data coherency
  • Significant system power savings by eliminating the external I/O paths between the processor and the FPGA

Flexible FPGA Fabric

The FPGA logic fabric lets you differentiate your system by implementing custom IP or off-the-shelf preconfigured IP from Altera or its partners into your designs. This allows you to:

  • Adapt quickly to varying or changing interface and protocol standards
  • Add custom hardware in the FPGA to accelerate time-critical algorithms and create a compelling competitive edge
  • Quickly deploy a custom ARM processor without the extensive design, verification, and non-recurring engineering (NRE) costs required in ASICs

Architecture Matters

Because Cyclone V SoCs integrate many hard IP blocks, you can lower your overall system cost, power, and design time. SoCs are more than the sum or their parts. How the processor and FPGA systems work together matters greatly to your system’s performance, reliability, and flexibility. Altera SoCs are designed to:

  • Preserve the flexibility of processor boot or FPGA configuration sequence, system response to processor reset, and independent memory interfaces of a two-chip solution
  • Maintain data integrity and reliability with integrated ECC
  • Protect DRAM memory shared by the processor and FPGA with an integrated memory protection unit
  • Enable system-level debug with Altera’s FPGA-adaptive debugging for unmatched visibility and control of the whole device

Not All SoC FPGAs Are Created Equal. Architecture Matters.

Learn how to choose the right SoC FPGA for your application from our extensive set of resources, including a short series of videos from processor expert Jim Turley.

Learn More >>

Comparison of Cyclone V SoC Variants

Features Cyclone V SE SoC Cyclone V SX SoC Cyclone V ST SoC
Processor
Dual-core ARM Cortex-A9 MPCore
Processor Performance
925 MHz
Logic Density Range
25 – 110K logic element (LE)
85 – 110K LE
Embedded Memory
5,761 kb
18 x 19 Multipliers
224
Maximum Transceivers
N/A
9
Maximum Transceiver Data Rate (Chip to Chip)
N/A
3.125 Gbps
6.144 Gbps
Memory Devices Supported (Hard Memory Controllers)
x1 32 bit, 400 MHz DDR2/DDR3 with ECC – HPS
x1 32 bit, 400 MHz, DDR2/DDR3 - FPGA
Hard Protocol IP
x2 10/100/1000 EMAC – HPS
x2 10/100/1000 EMAC – HPS
x2 PCIe Gen1 x4 - SX
x2 PCIe Gen2 x4 - ST
Family Overview Table
icon-cyclone-v-product-table

Architecture Matters
Architecture Matters

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