Stratix® 10 SoCs, manufactured on Intel’s 14 nm FinFET process technology, feature our third-generation hard processor system (HPS) based on a quad-core ARM® Cortex®–A53 processor cluster.  The hard processor system also includes a deep feature set of peripherals and is combined with the ground-breaking HyperFlex™ architecture to create the industry's highest performance SoC FPGA product family. 

Stratix 10 SoC Block Diagram

Notes:

  1. Integrated direct memory access (DMA)
  2. Integrated error correction code (ECC)
  3. Multiport front-end interface to hard memory controller

HPS: Quad ARM Cortex-A53 Hard Processor System
SDM: Secure Device Manager
EMIB: Embedded Multi-Die Interconnect Bridge

Stratix 10 SoC Feature Overview

See the tables below for an overview of the Stratix 10 SoC hard processor system features. All features in the HPS are common to all the SoC devices in the famlly.

Stratix 10 Hard Processor System (HPS) Features

Feature

Description

Processor

Quad-core ARM Cortex-A53 processor cluster up to 1.5 GHz

Coprocessors

Vector floating-point unit (VFPU) single and double precision, ARM Neon™ media processing engine for each processor

Level 1 Cache

32 KB L1 instruction cache with parity, 32 KB L1 data cache with ECC

Level 2 Cache

1 MB KB shared L2 cache with ECC

On-Chip Memory

256 KB on-chip RAM

System Memory Management Unit

System Memory Management Unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the  FPGA fabric

Cache Coherency Unit

Changes in shared data stored in cache are propagated throughout the system coherently providing bidirectional coherency for co-processing elements

Direct Memory Access (DMA) Controller

8-channel DMA

Ethernet Media Access Controller (EMAC)

3x 10/100/1000 EMAC with integrated DMA

USB On-The-Go Controller (OTG)

2x USB OTG with integrated DMA

UART Controller

2x UART 16550 compatible

Serial Peripheral Interface (SPI) Controller

4x SPI

I2C Controller

5x I2C

QSPI Flash controller

1x SIO, DIO, QIO SPI flash supported

SD/SDIO/MMC Controller

1x eMMC 4.5 with DMA and CE-ATA support

NAND Flash Controller

1x ONFI 1.0 or later 8 and 16 bit support

General-Purpose I/O (GPIO)

Maximum 62 software-programmable GPIO

Timers

7X general-purpose timers, 4X watchdog timers

Stratix 10 SX Family Table

Download PDF Family table
 
Part # Reference 10SX050
 
10SX065 10SX085 10SX110 10SX165
 
10SX210 10SX250 10SX280 10SX450 10SX550
Stratix 10 Product Line SX 500
 
SX 650 SX 850 SX 1100 SX 1650
 
SX 2100 SX 2500 SX 2800 SX 4500
 
SX 5500
Equivalent
LEs1
484,000 646,000 841,000 1,092,000 1,624,000 2,005,000 2,422,000 2,753,000 4,463,000 5,510,000

Adaptive Logic

Modules
(ALMs)

164,160 218,880 284,960 370,080 550,540 679,680 821,150 933,120 1,512,820 1,867,680
ALM Registers 656,640 875,520 1,139,840 1,480,320 2,202,160 2,718,720 3,284,600 3,732,480 6,051,280 7,470,720
Hyper-Registers from HyperFlex Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric
Programmable Clock Trees Synthesizeable Hundreds of synthesizable clock trees

Maximum
Transceiver
Count

24 24 48 48 96 96 144 144 72 72

GXT Full Duplex

Transceiver Count
(30 Gbps)

16 16 32 32 64 64 96 96 48 48

GX Full Duplex

Transceiver Count
(17.4 Gbps)

8 8 16 16 32 32 48 48 24 24
M20K Memory
Blocks
2,196 2,583 3,477 4,401 5,851 6,501 9,963 11,721 7,033 7,033
M20K Memory
(Mb)
43 50 68 86 114 127 195 229 137 137
MLAB Memory
(Mb)
3 3 4 6 8 11 13 15 23 29

Variable-Precision

Digital Signal Processing

(DSP) Blocks

1,152 1,440 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
18x19
Multipliers
2,304 2,880 4,032 5,040 6290 7,488 10,022 11,520 3,960 3,960
Fixed Point Peformance (TMACS)2 4.6 5.8 8.1 10.1 12.6 15.0 20.0 23.0 7.9 7.9
Single Precision Floating Point (TFLOPS)3 1.8 2.3 3.2 4.0 5.0 6.0 8.0 9.2 3.2 3.2
Maximum User I/O Pins 488 488 736 736 704 704 1160 1160 1640 1640
PCI Express®
(PCIe®) Hardened Intellectual
Property (IP)
Block(s) (up to Gen3)
1 1 2 2 4 4 6 6 3 3
Secure Device Manager
 
AES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protection
Hard Processor System4 Quad-core 64 bit ARM® Cortex®-A53 up to 1.5 GHz with 32 KB I/D cache, NEONTM coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general-purpose timers x7, watchdog timer x4
Notes:

All Stratix 10 SoC (SX) devices include the full set of HPS features.

Stratix 10 SX Package Options & I/O Pins (General-Purpose I/O Pins, High-Voltage I/O Pins, LVDS Pairs & Transceivers)

Download PDF Package Table1,2
Part # Reference 10SX050

10SX065 10SX085 10SX110 10SX165

10SX210 10SX250 10SX280 10SX450 10SX550
Stratix 10 Product Line SX 500

SX 650 SX 850 SX 1100 SX 1650

SX 2100 SX 2500 SX 2800 SX 4500

SX 5500

F1152 pin

35 mm

344, 8,

168, 24

344, 8,

168, 24

- - - - - - - -

F1760 pin

42.5 mm

488, 8,

240, 24

488, 8,

240, 24

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

- -

F2112 pin

47.5 mm

- -

736, 16,

360, 48

736, 16,

360, 48

- - - - - -

F2112 pin

47.5 mm

- - - -

648, 24,

312, 72

648, 24,

312, 72

648, 24,

312, 72

648, 24,

312, 72

- -

F2112 pin

47.5 mm

- - - - -

-

- -

648,24,

312, 72

648,24,

312, 72

F2397 pin

50 mm

- - - - - -

1160, 8,

576, 24

1160, 8,

576, 24

1256, 8,

624, 24

1256, 8,

624, 24

F2397 pin

50 mm

- - - -

704, 32,

336, 96

704, 32,

336, 96

704, 32,

336, 96

704, 32,

336, 96

- -

F2597 pin

52.5 mm

- - - - - -

432, 48,

192, 144

432, 48,

192, 144

- -

F2597 pin

55 mm

- - - - - -

1160,8,

576,24

1160,8,

576,24

1640, 8,

816, 24

1640, 8,

816, 24

Notes:
  1. A subset of pins for each package are used for high-voltage, 3.0 V and 2.5 V interfaces.
  2. Select devices available with pin migration from Arria® 10 device family to Stratix 10 device family. Contact us for more information.
  3. All data is preliminary, and may be subject to change without prior notice.

Dowload the Stratix 10 Device Family Table (PDF) to view the Stratix 10 FPGA and SoC family package plans with vertical migration support.