Intel® Stratix® 10 SoCs that are manufactured on Intel’s 14 nm FinFET process technology, feature our third-generation hard processor system (HPS) based on a quad-core ARM* Cortex*–A53 MPCore* processor cluster. The hard processor system also includes a deep feature set of peripherals and is combined with the ground-breaking Intel® HyperFlex™ FPGA Architecture to create the industry's highest performance SoC FPGA product family. 

Stratix 10 SoC Block Diagram

HPS: Quad-core ARM* Cortex*-A53 Hard Processor System
SDM: Secure Device Manager
EMIB: Embedded Multi-Die Interconnect Bridge

Intel® Stratix® 10 SoC Feature Overview

See the tables below for an overview of the Intel® Stratix® 10 SoC hard processor system (HPS) features. All features in the HPS are common to all the SoC devices in the family.

Intel® Stratix® 10 Hard Processor System (HPS) Features

Feature

Description

Processor

Quad-core ARM* Cortex*-A53 MPCore* processor cluster up to 1.5 GHz

Coprocessors

Vector floating-point unit (VFPU) single and double precision, ARM* Neon* media processing engine for each processor

Level 1 Cache

32 KB L1 instruction cache with parity, 32 KB L1 data cache with error correction code (ECC)

Level 2 Cache

1 MB KB shared L2 cache with ECC

On-Chip Memory

256 KB on-chip RAM

System Memory Management Unit

System Memory Management Unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the  FPGA fabric

Cache Coherency Unit

Provides one-way (I/O) coherency that allows a CCU master to view the coherent memory of the Cortex*-A53 MPCore* CPUs.

Direct Memory Access (DMA) Controller

8-channel direct memory access (DMA)

Ethernet Media Access Controller (EMAC)

3X 10/100/1000 EMAC with integrated DMA

USB On-The-Go Controller (OTG)

2X USB OTG with integrated DMA

UART Controller

2X UART 16550 compatible

Serial Peripheral Interface (SPI) Controller

4X SPI

I2C Controller

5X I2C

SD/SDIO/MMC Controller

1X eMMC 4.5 with DMA and CE-ATA support

NAND Flash Controller

1X ONFI 1.0 or later 8 and 16 bit support

General-Purpose I/O (GPIO)

Maximum 48 software-programmable GPIO

Timers 4X general-purpose timers, 4X watchdog timers
System Manager Contains memory-mapped control and status registers and logic to control system-level functions and other HPS modules.
Reset Manager Resets signals based on reset requests from sources in the HPS and FPGA fabric, and software writing to the module reset control registers.
Clock Manager Provides software-programmable clock control to configure all clocks generated in the HPS.

Intel® Stratix® 10 SX Device Family Table

 

Download PDF Family table
 

Part # Reference

1SG040

1SX040
 

1SG065

1SX065

1SG085

1SX085

1SG110

1SX110

1SG165

1SX165
 

1SG210

1SX210

1SG250

1SX250

1SG280

1SX280

1SG450

1SX450

1SG550 

1SX550

Stratix 10 Product Line

GX 400

SX 400
 

GX 650

SX 650

GX 850

SX 850

GX 1100

SX 1100

GX 1650

SX 1650
 

GX 2100

SX 2100

GX 2500

SX 2500

GX 2800

SX 2800

GX 4500

SX 4500
 

GX 5500

SX 5500

Equivalent
LEs1
378,000 612,000 841,000 1,092,000 1,624,000 2,005,000 2,422,000 2,753,000 4,463,000 5,510,000

Adaptive Logic

Modules
(ALMs)

128,160 207,360 284,960 370,080 550,540 679,680 821,150 933,120 1,512,820 1,867,680
ALM Registers 512,640 829,440 1,139,840 1,480,320 2,202,160 2,718,720 3,284,600 3,732,480 6,051,280 7,470,720
Hyper-Registers from HyperFlex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric
Programmable Clock Trees Synthesizeable Hundreds of synthesizable clock trees

Maximum
Transceiver
Count

24 48 48 48 96 96 96 96 24 24

GXT Full Duplex

Transceiver Count
(30 Gbps)

16 32 32 32 64 64 64 64 16 16

GX Full Duplex

Transceiver Count
(17.4 Gbps)

8 16 16 16 32 32 32 32 8 8
M20K Memory
Blocks
1,537 2,489 3,477 4,401 5,851 6,501 9,963 11,721 7,033 7,033
M20K Memory
(Mb)
30 49 68 86 114 127 195 229 137 137
MLAB Memory
(Mb)
2 3 4 6 8 11 13 15 23 29

Variable-Precision

DSP Blocks

648 1,152 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
18 x 19
Multipliers
1,296 2,304 4,032 5,040 6,290 7,488 10,022 11,520 3,960 3,960
Fixed Point Performance (TMACS)2 2.6 4.6 8.1 10.1 12.6 15.0 20.0 23.0 7.9 7.9
Single Precision Floating Point (TFLOPS)3 1.0 1.8 3.2 4.0 5.0 6.0 8.0 9.2 3.2 3.2
Maximum User I/O Pins 392 400 736 736 704 704 1,160 1,160 1,640 1,640
PCI Express* 
(PCIe*) Hardened Intellectual
Property (IP)
Block(s) (up to Gen3)
1 2 2 2 4 4 4 4 1 1
Secure Device Manager
 
AES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protection
Hard Processor System4 Quad-core 64 bit ARM Cortex-A53 up to 1.5 GHz with 32 KB I/D cache, NEON* coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general-purpose timers x7, watchdog timer x4
Notes:

All Intel® Stratix® 10 SoC (SX) devices include the full set of HPS features.

Intel® Stratix® 10 GX/SX Device Package Options and I/O Pins

Download PDF Package Table1,2
Part # Reference

1SG040

1SX040

1SG065

1SX065

1SG085

1SX085

1SG110

1SX110

1SG165

1SX165

1SG210

1SX210

1SG250

1SX250

1SG280

1SX280

1SG450

1SX450

1SG550

1SX550

Intel® Stratix® 10 Product Line

GX 400

SX 400

GX 650

SX 650

GX 850

SX 850

GX 1100

SX 1100

GX 1650

SX 1650

GX 2100

SX 2100

GX 2500

SX 2500

GX 2800

SX 2800

GX 4500

SX 4500

GX 5500

SX 5500

F1152 Pin

35 mm x 35 mm,

1.0 mm pitch

392, 8,

192, 24

392, 8,

192, 24

- - - - - - - -

F1760C Pin

42.5 mm x 42.5 mm,

1.0 mm pitch

-

400, 16,

192, 48

-

-

-

-

-

-

- -

F1760A Pin

42.5 mm x 42.5 mm,

1.0 mm pitch

- -

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

- -

F2112 Pin

47.5 mm x 47.5 mm,

1.0 mm pitch

- -

736, 16,

360, 48

736, 16,

360, 48

-

-

-

-

- -

F2397 Pin

50 mm x 50 mm,

1.0 mm pitch

- - - -

704, 32,

336, 96

704, 32,

336, 96

704, 32,

336, 96

704, 32,

336, 96

- -

F2597 Pin

55 mm x 55 mm,

1.0 mm pitch 

- - - - - -

1160,8,

576,24

1160,8,

576, 24

1640, 8,

816, 24

1640, 8,

816, 24

Notes:

1. A subset of pins for each package are used for high-voltage, 3.0 V and 2.5 V interfaces.
2. Select devices available with pin migration from Intel® Arria® 10 device family to Intel® Stratix® 10 device family. Contact us for more information.
3. All data is preliminary, and may be subject to change without prior notice.

Download the Intel® Stratix® 10 Device Family Table (PDF) to view the Intel® Stratix® 10 FPGA and SoC family package plans with vertical migration support.